CAMBRIDGE, UK — Synopsys announced a new capability in its DFTMAX compression to reduce the cost of test for designs and methodologies that mandate very few test pins.
Extending the patented adaptive scan technology with a high-performance, low-pin interface to the tester allows designers to achieve predictable compression of up to 100x or more with only one pair of test data pins, claims the EDA company.
As designers must maintain test quality and reduce test cost while design complexity is growing, they increasingly adopt core-based design and test methodologies as well as multi-site testing techniques, significantly limiting the number of pins allocated for test.
"Timely delivery of highly reliable products to our customers is essential for our success," said Jean-Louis Cols, vice president of product development at Wolfson Microelectronics. "To meet our quality goals and lower the cost of production testing, we continually strive to maximize test coverage and minimize test data volume and test time whilst considering the capabilities and limitations of the target tester platform.
DFTMAX compression and TetraMAX ATPG have repeatedly allowed us to achieve these goals for our latest mixed-signal designs. The new enhancements in DFTMAX compression for pin-limited test give us the full benefits of compression on our lowest pin-count mixed-signal designs."
The high-speed, low-pin tester interface generated by DFTMAX compression serializes the test data, enabling up to 100X or more test data volume and test application time reduction for these pin-limited test methodologies.
DFTMAX compression and TetraMAX ATPG are built into the Galaxy implementation platform
More info at www.synopsys.com
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