Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) claims that it has developed the first functional 64-Mbit SRAM cell, based on its 28-nm technology. This development was presented in a paper at the 2009 Symposia on VLSI Technology and Circuits in Kyoto, Japan.

TSMC (Hsinchu, Taiwan) recently announced the 28-nm process, which allows an option for silicon dioxide or a high-k/metal-gate scheme for the gate stack.

The paper does not appear to discuss high-k. Instead, the paper outlines a low-power technology that extends silicon oxynitride (SiON)/poly usage beyond 32-nm with a dual/triple gate oxide process.

Other characteristics from this technology includes 6-T SRAM cells, low leakage transistors, conventional analog/RF/electrical fuse components, copper interconnects and low-k.

The paper also reports a 64-Mbit SRAM with a cell size of 0.127-um², and a raw gate density as high as 3900 kGate/mm² in this 28-nm dual/triple gate oxide SoC technology. In the paper presented, low standby and low operating power transistors using SiON optimized with strain engineering and oxide thickness provide up to 25-to-40 percent speed improvement or 30-to-50 percent active power reduction over prior 45-nm technology, according to TSMC.

''This development was achieved through close collaboration with customers who are pushing their own boundaries of new applications requiring 28nm technology," said Jack Sun, vice president R&D at TSMC,'' in a statement.

In the previous announcement made in September 2008, TSMC plans to deliver its 28-nm process in early 2010.

Amid one of the toughest periods in its illustrious history, TSMC remains cautiously optimistic about the IC industry and vowed that it will continue to invest in R&D despite the downturn. And it is also planning to move the IC-equipment in its R&D fab for the 22-nm node.