SAN JOSE, Calif.—The IC design community often ignores the manufacturing side of the house, especially the arcane world of lithography.
During a keynote address at the SPIE Advanced Lithography conference on Monday (Feb. 23), Lisa Su, senior vice president and general manager of networking and multimedia and chief technology officer for Freescale Semiconductor Inc. (Austin, Texas), bucked the trend and asked the EDA and lithography communities for help.
''Design complexity is out of control,'' Su said. ''Help us simplify our lives.''
If design complexity is not simplified, Su predicts a troubling trend. ''Without improvement in this area, we will see fewer designs,'' she warned.
On the manufacturing and EDA fronts, she cited several problems for IC designers: litho-induced complexity; design-for-manufacturing (DFM) and EDA tool complexity.
As design rules shrink, more cost and complexity are introduced into chips. Lithography is part of the problem. Among the elements in ''litho-induced complexity'' include optical proximity correction (OPC), phase shift masks, and, more recently, source-mask optimization (SMO). SMO is an element of computational lithography, which is geared for the 22-nm node.
EDA tools are also becoming more complex and expensive. DFM, for example, remains a stumbling block. Part of the DFM flow includes lithography aware tools, resolution enhancement techniques (RETs), mask and yield.
''It's getting very, very, very expensive,'' she said. ''Full DFM is a challenge. It takes weeks for that to happen (in IC designs). That's unrealistic.''
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