Intel, which outlined its lithography roadmap, also warned that current 193-nm immersion technology with double-pattering techniques will soon run out of gas, possibly at 20-nm or sooner. This will require new solutions like EUV, but challenges remain for this and other next-generation lithography (NGL) technologies.

The microprocessor giant hopes to insert EUV at the later stages of the 22-nm node, but it is more likely to use the technology at the 15-nm node (26-to-30-nm half-pitch) in 2013 or so. Originally, EUV was targeted for the 65-nm node, but the technology has been pushed out due to the lack of power sources, resists, defect-free masks and other technologies.

''We are pushing hard on EUV,'' said Sam Sivakumar, Intel fellow and director of lithography for the chip giant, at an event hosted by Nikon Corp. ''Significant progress has been made.''

But besides the usual issues, there are more ''technical gaps'' in EUV. To enable EUV in mass production fabs, IC makers must get their hands on defect-free photomasks. The trouble is that the industry is far behind in the development and funding of EUV-based inspection tools, mask blank inspection gear and fab reticle machines, he said.

In terms of R&D, EUV inspection gear is projected to cost $150 million, blank inspection gear is about $50 million and fab reticle machines is $10 million. Right now, tool makers face a major downturn and R&D dollars remain scarce.

Intel is pushing other chip makers and consortiums like Sematech to drive tool development. "We are working very hard'' to develop the EUV inspection infrastructure, he said, but ''we need more support.''

The two main EUV tool developers--ASML Holding NV and Nikon--are separately pushing EUV technology for the 32- or 22-nm nodes. KLA-Tencor, Rave and others are working on EUV inspection and repair.

Reports have surfaced that Samsung Electronics Co. Ltd. may attempt to use EUV for DRAM production at the 45-nm node or below. But Intel, the big proponent for EUV, will not use the technology in logic for some time.

At 45-nm, the chip giant is using 193-nm ''dry'' scanners, reportedly from both ASML and Nikon. Recently, Intel rolled out the details of its 32-nm process (56-nm half-pitch), with initial devices expected to be shipped by year's end. The company also said it will spend $7 billion in fab upgrades for 32-nm production.

At 32-nm, Intel will insert its initial immersion scanners, that is, 193-nm wavelength technology. At the node, the company will use single-exposure technology--and not double patterning, Sivakumar said. At 32-nm, Intel reportedly will use one lithography vendor, Nikon, as previously reported.