Current design styles are precise and minimalistic. As a result efforts to make chips more reliable frequently involve redundancy, which involves higher costs and reduced speed of calculation. As the miniaturization of electronics continues product lifetimes will become dangerously short, without innovative approaches to address in-field silicon failures, the SRC said.

Meanwhile building faultless chips is becoming increasingly difficult with millions of dollars wasted each time a chip design is respun, sometimes for the sake of one or two transistors out of hundreds of millions.

The research project is intended to investigate a defect-tolerant design style that could increase product lifetime through components that take longer to fail or which can recover from failure, according to the SRC.

The research will entail the development of silicon- and system-failure models, and a modeling infrastructure that would allow designers to better understand the reliable system design space and to evaluate the robustness of potential solutions.

"The solution is not to build flawless chips, but architectures that can survive defects," said Todd Austin, associate professor of electrical engineering at University of Michigan and a former Intel design engineer. Valeria Bertacco, co-investigator and an assistant professor at the University of Michigan, added: "We've not given up on making semiconductors always correct. Rather, we're facing up to the looming problem in the chip industry — smaller switches and wires don't always work."

"In this project, we'll go much further than before by designing chips that can diagnose when components wear out and heal themselves on the fly," said Sankar Basu, program director at the NSF.

SRC and NSF selected the University of Michigan's team to fund for three years. The SRC did not say how large a budget would be assigned to the "self-healing" chips project.