Paolo Gargini, Intel's director of technology strategy and Intel Fellow, confirmed that Intel would make use of the EUV stepper installed at the IMEC European research organization for research purposes, at least initially.

The appropriate time for EUV lithography to be used commercially is widely held to be the 32-nanometer manufacturing process node due to debut around 2009 or 2010. This is where EUV stands on the International Technology Roadmap for Semiconductors (ITRS) of which Gargini is chairman. "The number one choice for 2010 was EUV," said Gargini at a press meeting here implying that EUV would not only be successfully introduced but would eclipse the immersion lithography that is now looking necessary for manufacturing at the 45-nm manufacturing node.

"Lithography must break through to the shorter wavelength of13.5 nanometer," he said. "Activity on our side started in 1996. But we also take part in research elsewhere."

Gargini said there are two EUV alpha tools nearing completion that would be shipped in the first quarter of 2006. One would go to IMEC and the other to Albany, Gargini said.

"In the first quarter the first fully integrated EUV lithography machine will be delivered to IMEC at Leuven. And as we are members [of industrial affiliation programs] we'll make use of it."

ASML is the key to that industrial affiliation program on lithography. In addition ASML, working in collaboration with IBM Corp. and New York State, announced plans to invest $400 million, in a research center at the University of Albany, ASML's first outside of Europe, in Jan. 2005.

Peter Kuerz, senior EUV systems manager for Carl Zeiss SMT AG, confirmed that his company is working on the lenses for two EUV alpha tools under construction.

Intel also has its own micro-exposure tool, delivered to Intel in October and which looks like a small submarine, Gargini said, and activity in EUV had shown progress in certain key areas, he said.

"In the last six months we've seen reports of a 40-watt optical source. We believe we will be able to get in to the 100-watt regime, needed for commercial wafer throughput," Gargini said.

Gargini also showed data with EUV blank masks with the number of defects reduced to optical lithography levels. "The EUV masks are done in Santa Clara and then sent to Oregon, where the submarine is." In 2009 we expect a production machine at 80 to 100 wafers per hour to be available.

Intel joined a major IMEC industrial affiliation program on advanced lithography as a core partner in October 2003.