An SRAM memory cell was made with non-conventional lithography and is claimed to be 43 percent smaller than the size of the previously reported smallest SRAM cell.

Researchers from the National Nano Device Laboratories (Taiwan) and UC-Berkeley built a functional 0.039m2 six transistor SRAM cell using a maskless, photoresist-free, nano-injection lithography technique.

The nano-injection lithography employs a gas-phase chemical reaction — activated with a finely controlled electron beam — to deposit a desired nanometer-scale hard mask pattern for subsequent etching.

The reaction can deposit both dielectric and conductive masking materials.

The lithography process incorporates a full TiN gate and dynamic supply-voltage regulator, and promises to be a low-cost way to perform device and circuit verification for 16-nm technology development, according to the researchers from National Nano Device Laboratories and UC-Berkeley.

Meanwhile, another late paper by Penn State, Cornell and IQE Inc. researchers will describe an interband tunneling field effect transistor (TFET) built on InGaAs. It features on-current of 20uA/um at 0.75V and a large on-off current ratio of 104.

The device channel length is 100nm.

The team achieved this performance by fabricating a gate-modulated Zener tunnel junction at the source, to provide for a more abrupt current turn-on. In addition, the vertical architecture allowed for high-quality in-situ doped junctions that reduce leakage when the device is off.

The researchers built a 6T SRAM memory cell, which demonstrated excellent read/write noise margins down to a 0.3V supply voltage.

The 55th annual IEEE International Electron Devices Meeting will be held at the Hilton Baltimore on December 7-9. Some 215 papers will be given by researchers from corporations, universities and government labs worldwide.