Intel showed Larrabee handling ray tracing in real time on a next-generation PC. The technique is used to show realistic light effects such as shadows and reflections

Intel would not say when it plans to release Larrabee which is expected compete with graphics chips from AMD and Nvidia. When Larrabee was described last year, Intel said it could ship in 2009.

A software developer's kit is already available for Larrabee which can be programmed in a manner similar to today's multicore x86 processors. In addition, Intel held several classes at IDF on new vector-processing instructions coming for a next-generation CPU called SandyBridge, expected to debut late next year.

In the demo, Intel showed the Larrabee chip running on an adapter card in a prototype system using Golftown, a high-end desktop CPU that will ship in 2010. Golftown uses six dual-threaded cores.

Separately, Intel demonstrated hardware support in its next-generation 32nm Westmere CPU architecture for the AES security algorithm. Westmere chips will have seven new instructions and small hardware blocks for accelerating AES processing as much as twelve-fold, Intel said.

The x86 giant also recommitted to its Itanium architecture at IDF. Intel now has three future Itanium chips in design, including the much delayed Tukwilla version which will ship earlier next year. Tukwilla is the first Itanium chip to share with Intel's mainstream Xeon processors common elements including the Quick Path Interconnect, chip sets and DDR3 memories.

At the card level, Intel rolled out a reference design for a server on an adapter about the size of a 4x7 index card. The so-called microserver targets data center applications that demand both high density and hardware isolation.

Serial entrepreneur Andy Bechtolsheim said the microserver was an interesting product that could pack as much power as previous two-chip servers. However, he expressed concern the microserver would be limited by the amount of ECC memory it could support.

In the embedded space, Intel discussed its recently announced Jasper Forest chip. It includes two Xeon-class processors, 5 GHz PCI Express, a non-transparent Express bridge and hardware support for RAID levels 5 and 6.

Hewlett Packard said it will use Jasper Forest in future storage arrays. China OEM ZTE will use it in wireless infrastructure gear and Nokia Siemens Networks also plans to use the device.

In a talk about silicon technology, Intel suggested it might explore using III-V materials to create high-speed channels in CMOS in future process technologies. Jesus Del Alamo, a professor of electrical engineering at MIT, discussed his work in the area and his belief the III-V materials could double the speed of some operations while cutting voltage rates in half.