In February this year Laurie Balch, a Gary Smith EDA analyst, said in an article written for Solid State Technology that "because an ESL-based methodology involves bridging between IC designers, system designers, and embedded software designers — groups with traditionally different design needs and tool budgets — developing a full-fledged ESL flow is no small task."

Indeed. The forecasts of 2005 were swallowed by the current recession.

But it may be more than a recession problem.

Balch said in part, "creating a full suite of ESL technologies will be a necessary step for EDA to keep adequately serving electronics designers through future semiconductor generations."

So how will ESL change the EDA industry?

In his predictions before DAC 2009, industry watcher Geoffrey James wrote that "the promise of ESL was continually scuttled by the demands of ever-more-complex manufacturing process." He then provided six design trends that point to ESL coming into its own.

The System-on-Chip virtual conference to be held Wed. Sept. 16 should shed more light on the subject.

As for me, I can only welcome a system-level approach to chip design. As more designs go into mobile applications there will be a need to both design at a higher abstraction level as well as reduce the power of powerful chips in small spaces.

Recently ChipVision Design Systems authors showed the ability to reduce power consumption by up to 75 percent at the Electronic System Level, which has spawned new interest in solving power issues at that level.

In other words, ESL is seen by many as the best opportunity to reduce the power consumed by a system.

As site editor of both EDA DesignLine and Power Management DesignLine, this notion brings a welcome smile on my face.

What do you think? Will ESL finally take off? Is the ESL methodology a panacea for power-efficient IC designs?

We want strong opinions on the subject. Has the ESL methodology in chip design become a requirement for next-generation chips. I say yes. What do you say?