The fundamental definition of a SoC is a device that contains one or more processor cores and some on-chip memory coupled with a mixture of hardware accelerator functions, peripheral and communications functions, and often some analog/mixed-signal content.

There are two ways to implement an SoC. The first is to create a new chip from the ground up using an ASIC/ASSP design flow. A more recent alternative is to implement a programmable SoC (PSoC) using one of today's sophisticated FPGAs.

Representing the FPGA-based SoC approach during the forthcoming EE Times SoC Virtual Conference System-on-Chip: Designing Next Generation SoCs) is keynote speaker Gerry Gaffney, president of Altium USA.

In a keynote presentation, "Beyond ASIC-based SoCs," Gaffney will discuss the design approach and tool systems needed to allow all parts of the design process to work together in a flexible and constructive way, and in the process exploit the full potential of FPGA-based SoCs. The approach transcends the constraints of traditional ASIC-based SoC or hardware-centric design by harnessing FPGAs as a highly flexible system platform that, along with hosting soft devices in the familiar sense, can form a soft-hardware interface layer and connectivity backbone for the entire design. This opens up a new approach to system-level electronics design that provides the design freedom and flexibility needed to create tomorrow's innovate products.

Representing the ASIC-based SoC approach is keynote speaker Rajeev Madhavan, CEO and co-founder of Magma Design Automation. In his keynote presentation, "Deriving ROI from Next-Generation SoCs," Madhavan will outline what it takes to make SoC design profitable. He'll describe the changes that are needed in both design tools and licensing models. He'll also explain how to improve the productivity of analog and mixed-signal designers, how to leverage higher levels of automation and faster verification to speed turnaround time and what it takes to enable analog design reuse. He'll also discuss how changes to software licensing models will benefit both designers and software providers.

The EE Times Virtual Conference will take place on Sept. 16. The event will feature presentations and panel discussions designed to explore the challenges faced by developers of ASIC- and FPGA-based SoCs, including a series of panel discussions focused squarely on this topic.