DAC attendance highlights recessionary times
Preliminary attendance figures at this year's Design Automation Conference show an increase in total conference and exhibit attendance by 12 percent over last year's DAC held in Anaheim, Calif. and by three percent over the 2007 San Diego event. The preliminary figures break down into 3247 attendees for the DAC Exhibit-Only Monday and 1,888 attendees signed up for this week's DAC Technical conference (workshops, tutorials, etc.). Final adjusted attendance numbers will be coming next month. (See separate story).

Mentor Graphics unveils embedded Linux strategy
Mentor Graphics has expanded its position in embedded software with the unveiling of its Android and Linux strategy at the Design Automation Conference. The EDA vendor has also announced the acquisition of Embedded Alley Solutions, a leader in Android and Linux development systems. Embedded Alley's Android and Linux products and services will be offered with the Mentor Graphics Nucleus real-time operating system, tools and middleware. Mentor Graphics is planning to provide solutions beyond the mobile market for which Android was originally developed. (See separate story).

Nvidia's chief scientist wants power tools
Nvidia Corp.'s chief scientist told the EDA community Wednesday (July 29) that chip designers need new tools to usher in a new era, moving to "throughput computing" from an era of "denial architecture" that has seen the semiconductor industry squeeze more performance out of single-thread processors thanks to software. Delivering a keynote address here at the Design Automation Conference, William J. Dally, chief scientist and senior vice president of research at Nvidia and an engineering professor at Stanford University, said computing is entering a world where performance increases are derived from parallelism and efficiency is determined by locality. (See separate story).

DFM debated as a 'weapon of mass design'
The more than abused DFM acronym reared its ugly head again at a leading design engineering forum. The consensus is that design for manufacturing has its place in the chip design world, but basically it's a crapshoot. "It's a band aid with diminishing returns," said Kimon Michaels, VP Design and co-founder at PDF Solutions. "At the leading edge of chip design, new materials and reduced line width margins require that manufacturing be considered as part of the design cycle." (See separate story)

TSMC exec touts cooperation
Future growth in EDA and other segments of the semiconductor industry supply chain depends on the evolution of a new breed of collaborative business model that enable partners to pool costs and increase profits, according to Fu-Chieh Hsu, vice president of Design & Technology Platform at leading foundry Taiwan Semiconductor Manufacturing Co. (TSMC). Delivering a keynote address at the Design Automation Conference here Tuesday (July 28), Hsu said a community business model with tight partnerships could enable TSMC and ecosystem partners to collectively create greater value and get better returns by collaborating to reduce waste, development costs and maintenance overhead. (See separate story).

Virage Logic tapes out its first 32/28nm IP test chip
Virage Logic has taped out a 32/28-nanometer process node test chip with multiple IPs optimized for a high performance application for an early adopter customer. In addition to the product test chip, Virage Logic has also taped out multiple 32nm test chips at leading foundries. According to Virage, the early adopter customer selected Virage Logic to leverage the power management capabilities of the SiWare Memory compilers and advanced embedded memory test and repair capabilities of the Star Memory System for their first 32/28nm chip. (See separate story).

CEOs debate EDA's fair share
The age-old question of whether EDA gets its fair share of semiconductor ecosystem revenue reared its head at a panel discussion involving the CEOs of EDA's three largest companies, with Aart de Geus of Synopsys suggesting that the current recession may be the catalyst for a favorable change. (See separate story).

Cadence adds more IP products to Xuropa Online Labs
Cadence Design Systems Inc. has increased the number Incisive verification IP products available within Xuropa Online Labs, a cloud-computing application that makes available existing software applications through a software-as-a-service model. Users can run simulations and employ the verification IP on example circuits at their convenience from their desktop, the company said. With only a web browser, approved visitors to Xuropa Labs can access the Cadence Incisive verification IP components for several protocols.

Galaxy 2009 boasts 2X faster throughput, Synopsys says
Synopsys Inc. Tuesday (July 28) announced the latest release of its Galaxy implementation platform, which the company said offers 2X faster design implementation and signoff throughput with new multicore performance and multi-corner/multi-mode technologies. The Galaxy 2009 release is available now, according to Synopsys.

Magma announces new release of Titan mixed-signal design platform
Magma Design Automation announced a new release of the Titan mixed-signal design platform, which now includes the Titan Analog Simulation Environment and Titan Schematic-Driven Layout tools. Several productivity enhancements have also been made to the existing Titan Schematic Editor, Titan Layout Editor and Titan Shape-Based Router, Magma said. Titan is billed as the first truly unified, open platform that embeds digital standard-cell design into the analog circuit design flow, according to Magma. The new release of the Titan mixed-signal design platform will be available next month, Magma said.

Magma hit with 'going concern' notice
Troubled EDA vendor Magma Design Automation Inc.'s independent auditor has raised questions about the company's ongoing viability, Magma said Monday (July 27). The accounting firm, Grant Thornton LLP, issued a "going concern" qualification, filed along with Magma's annual report for the period ended May 3, Magma (Santa Clara, Calif.) said. A going concern qualification is a reflection of the auditor's concern about the company remaining in operation. (See separate story.)

Mentor rolls architecture-level power tool
Mentor Graphics Corp. introduced the Vista platform for architecture design and prototyping, enabling users to model, analyze and optimize power at the transaction level of abstraction. Mentor said the platform enables engineers to model power at the transaction architecture level using advanced power estimation policies long before an implementation becomes available, or annotate more accurate power behavior based on attributes of the technology process of the target implementation IP blocks. Optimization at the electronic system level (ESL) can result in power savings of 80 percent, as opposed to less than 20 percent at the synthesis, gate and layout levels, according to Mentor executives. When intellectual property (IP) vendors begin to provide power transaction-level power models with IP it will spur a larger migration to ESL design, said Guy Moshe, general manager of Mentor's ESL/HDL Design Creation division.(See separate story).

Synopsys joins Common Platform, ARM for 32/22nm designs
ARM, Chartered Semiconductor Manufacturing, IBM, Samsung Electronics and Synopsys announced an agreement to develop a "comprehensive technology enablement solution" for the design and manufacture of mobile Internet-optimized devices. According to the partners, the objective of the collaboration is to leverage material science and SoC design for advanced mobile products. Synopsys' Lynx Design System will serve as the design environment for producing test chips. All three organizations are showing 32nm test chips from this ongoing effort at DAC. (See separate story).

Cadence validates ARM Libraries for 45-nm SOI process
Cadence Design Systems Inc. said it has validated a new generation of ASIC libraries from ARM using the Cadence Encounter Digital Implementation System, targeting IBM's 45-nanometer silicon-on-insulator (SOI) manufacturing process. The ARM 45-nm SOI libraries were developed using the Virtuoso custom design platform 6.1, Cadence (San Jose, Calif.) said.

Atrenta extends platform for chip architecture designs
Atrenta Inc. has made major extensions to its 1Team-Genesis platform, which supports architectural level chip assembly. The announcement includes enhancements to the existing 1Team-Genesis Assembly product and the introduction of two new products: 1Team-Genesis IO and 1Team-Genesis Registers. Enhancements to 1Team-Genesis Assembly include support for IP-XACT version 1.4, complete RTL import from either Verilog or VHDL and extensive support for hierarchical design management and editing. (See separate story).

Calypto offers 'full design flow' for SoC IP blocks
Calypto Design Systems Inc. is offering what it labels as a fully automated design flow aimed at IP blocks in SoC designs and is showing it at the Design Autmation Conference. Calypto's Sequential Optimization Flow allows designers, for the first time, to use a fully automated flow to optimize power, area and timing for high-performance IP blocks, such as microprocessors and DSPs, according to the company. (See separate story).

OSCI reports on its progress at DAC
The Open SystemC Initiative is reporting milestones achieved by three of its working groups at the Design Automation Conference here. OSCI is advancing SystemC as an industry-standard language for ESL design. The Transaction-level Modeling Working Group the Synthesis WG and the Analog/Mixed-Signa WG, all have made significant progress in meeting its goals. The TLM WG has completed a TLM-2.0 Reference Manual for public release. The manual is a formal description of the TLM-2.0 APIs and semantics. (See separate story).