Meanwhile, engineers are also working through new challenges using the virtual I/O standards the PCI SIG released at its conference last year. And others are working on an updated version of a PCI Express cable supporting data transfers at up to the 5 GHz rate of PCIe 2.0.

"The big news is PCI Express version 3.0 will be available in the first half of next year," said Al Yanes, president of the PCI SIG in a press briefing here.

Al Yanes President, PCI Special Interest Group

The new interconnect is expected to start shipping in systems in 2011. It initially will be used for bandwidth-hungry graphics chips in high-end desktops and in servers using multiport 10 Gbit Ethernet and 8 Gbit Fibre Channel cards.

The spec is expected to be in a version 0.7 this quarter. From that point, engineers will be running simulations and test chips to validate theoretical models of the technology. A separate test specification is also in the works.

When the work is complete, the 8 GHz interconnect is expected to be compatible with the previous 2.5 and 5 GHz versions and use the same connectors. It also is expected to support the existing PCIe bit-error rates and the reach of up to 20 inches and two connectors for servers.

The SIG chose 8 GHz rather than 10 GHz for PCIe 3.0 as a power saving measure. The additional equalization required to hit 10 GHz would have required "exponentially" more power, Yanes said.

"The power shot off the roof," in 10 GHz PCIe simulations, he said.

That decision forced developers to use a more aggressive 128b130b scrambled encoding scheme to maintain a doubling of throughput for the new generation interconnect to a Gbyte/second per lane in a single direction. The new encoding approach has just 1.6 percent overhead on data transmissions compared to 20 percent for the existing 8b10b encoding scheme.