Processor vendors are planning support for thread-level speculation and transactional memory as two ways assist developers in getting more parallelism. But it will require a new generation of domain-specific languages still in an early research phase before the average programmer can harness the parallelism in tomorrow's many-core chips, said Kunle Olukotun who directs the Pervasive Parallelism Lab at Stanford.

Both Intel and Sun aim to support transactional memory in hardware in future processors, said Olukotun in his keynote. "The question is how the software will develop to take advantage of transactional memory hardware," he said.

Pervasive Parallelism Lab's Director Kunle Olukotun

The technique, originally developed by database specialists, essentially groups multiple memory accesses into a single mega-transaction that is executed—or aborted—as a single task. With hardware support, the technique can deliver as much as a seven-fold performance improvement for some applications compared to software-only implementations, he said.

But "transactional memory doesn't solve all the problems," he said. "We still haven't addressed how we find independent tasks, map them to threads and optimize the locality and communications [of data] to provide predictable and scalable performance," added Olukotun, a professor of electrical engineering and computer science at Stanford.

To meet those goals, researchers are working on domain-specific languages that provide a level of abstraction. The languages would let programmers focus on defining applications-level jobs that the languages translate into parallel tasks.

SQL, MatLab, Ruby on Rails and OpenGL serve similar functions today for their targeted user groups. Olukotun said he hopes his lab can deliver a platform as early as 2012 to help create such tools.

"We want to make [parallel programming] practical for the masses of programmers," he said.

He also discussed thread-level speculation, a near term technique for reducing the need to synchronize tasks running in parallel. With hardware support, the technique can deliver significant performance gains, he said, showing results of an automated translator of x86 binary code into parallel software.

Some chip makers will support the technique within two or three years, he predicted. However, the technique is limited by its inability to scale.

The Multicore Virtual Conference continues until 6 pm Eastern time Thursday (June 18).