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Toshiba applies germanium to 16-nm MISFET gate stack
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EE Times Europe


LONDON — Toshiba Corp., claims to have developed a novel high-k dielectric gate stack with high carrier mobility that can be applied to metal-insulator-semiconductor field-effect transistors (MISFETs) in future generations of integrated circuits.

Toshiba has added a strontium germanide (SrGex) interlayer for application in MISFETs at the 16-nm node and beyond.

Current MISFET uses silicon for the channel, but physical limitations of silicon will make it difficult to obtain sufficient drive current in future scaled down MISFETs. Germanium has long been known as an alternative to silicon, offering higher carrier mobility characteristics. Development of gate stack structures for Ge-MISFETs is one of the challenges. There are reports of achieving high hole-mobility by adopting germanium dioxide (GeO2) in the gate stack insulating layer, but due to its low dielectric constant, there still remains the challenge of reducing the effective oxide thickness to 0.5-nanometers, which is required for the 16-nm node and after.

Toshiba claims to have overcomes the twin challenges of fabricating a thin gate stack while maintaining high hole mobility, by inserting SrGex as an interlayer between the high-k insulating layer and the germanium channel.

Germanium is first subject to heat surface treatment in an ultra-high vacuum, and a layer of strontium of up to ten atoms is deposited on the surface of the germanium, followed by a lanthanum aluminate high-k film. Finally, the gate stack is annealed in a nitrogen atmosphere. The SrGex layer is formed during these processes, between the high-k film and the germanium channel. The new technology realizes peak hole mobility of 481 centimeter squared per volt-second, a record high value for high-k/Ge p-MISFETs. This value is over three times than that obtained without the SrGex interlayer, and over twice the universal mobility that can be realized with silicon based on comparison with the same gate field, the company said.

Toshiba also said that a gate stack structure with an EOT of around 1-nm was formed, and that the increase in EOT by inserting the SrGex interlayer was a maximum of 0.2-nm. This suggests the possibility of further EOT scaling to 0.5-nm, either by reducing thickness of an overlaying high-k layer or adopting a high-k layer with a higher dielectric constant.

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