BANGALORE, India — A joint research team from Infineon Technologies and the Indian Institute of Technology, Bombay, is claiming an advance in the integration of high-voltage functionality for advanced CMOS technologies.

The joint program, launched in 2007, focuses on advanced research into the areas of I/O device design and multi-gate MOSFETs for sub-45-nm node CMOS technologies.

The joint team was able to explain the mechanisms behind electrostatic discharge (ESD) in high-voltage FET devices. Weak ESD robustness against exposure to high ESD stress had been an obstacle to the fabrication of high-voltage interfaces at 10 V and beyond in advanced CMOS technologies, the researchers said.

The researchers' insight into the physics of high-voltage devices could allow optimization of the layout of high-voltage I/O devices.

Based on their findings, the researchers said high-voltage functionality for devices ranging from USB interfaces to high-voltage line drivers could be integrated into system-on-silicon CMOS devices at 45 nm and below.

"The collaboration has been very helpful to us in understanding the complex nature of some of the existing device reliability issues, and the solutions proposed significantly improve our products," said Harald Gossner, senior principal engineer for ESD research at Infineon.

— K.C. Krishnadas is site editor of TechOnline India.