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Intel, NEC show diverging CPU paths
Stacked memory route vies with system-on-chip
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EE Times


SAN FRANCISCO, Calif. — Intel detailed its most highly integrated CPU to date at the International Solid State Circuits Conference (ISSCC) here Monday (Feb 9). A separate paper from NEC showed a promising approach to building processors out of stacked memory and logic chips.

The two papers raised the question of whether the future of microprocessors will be down the system-on-chip or system-in-package road. While that issue gets debated, Intel's dominance in microprocessors is increasingly apparent.

Intel supplied four of eight papers at the session where NEC's paper was the only other to generate a buzz. "It was a dry year," said Krste Asanovi, a computer science associate professor at Berkeley.

The gap between Intel and its rivals Advanced Micro Devices, IBM and Sun Microsystems is expected to widen. One rival remarked with amazement that, despite the deep recession, Intel still plans to ship 32 nm CPUs in 2009.

"We probably will not do that until 2011," said the engineer who asked not to be named.

In one of its papers Intel described Nehalem-EX, a 2.3 billion transistor server CPU, a member of its 45 nm Nehalem family expected to ship this fall. The chip includes eight cores supporting dual threading, two memory controllers and four 6.4 GigaTransfer/second point-to-point interconnects to create direct links between multiple CPUs in a high-end server.

The architecture mirrors that of archrival AMD which integrates memory controllers and the HyperTransport interconnect on its CPUs. Intel's QuickPath Interconnect (QPI) is "the biggest platform change Intel has made in 10 years," said Rajesh Kumar, an Intel architect who gave a separate paper on the Nehalem family.

Intel spent much of its time discussing its techniques for low power consumption on processors such as the Nehalem-EX which dissipates up to 130 W. The processor uses three separate voltage and clock domains to optimize control of its cores, I/O and non-core areas. It can also disable unused QPI ports in idle power to save on average about 2W per disabled port.

Nehalem also marks a shift away from fast domino circuits used for the previous CPUs to more power efficient static circuits.

"In the 1990's our focus was on performance at all costs," said Kumar. "We built circuits that were inherently faster, but they were burning a lot of power for small gains. With Nehalem we could not afford that anymore," he added.



Page 2: Stacking up a new approach to processor memory

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Related Links:

  • Top 10 Lies About Microprocessors
  • ISSCC 2009: A Chip-Stacked Memory for SoCs and Processors":
  • ISSCC 2009: A 45nm 8-Core Enterprise Xeon Processor



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