The Amba bus "has been around a long time so it's a pretty simple structure with a limited number of wires and control signals to connect cores," said Frank Ferro, director of business development at Sonics. "As you get designs with more cores and data throughput you wind up with a multilayer bus and more complexity."

With SNAP, chip designers simply specify the parameters of a given core's interface—such as its data rate and width—and the tool automatically generates the RTL for an on-chip interconnect. In this way, the tool eliminates the job of developing arbitration schemes, bridging protocols and other work for a designer building a multi-core ASIC.

"We are taking that work away from the design team and turning interconnect into a black box," said Ferro.

Sonics claims its approach can deliver on-chip interconnects that offer higher performance and lower power consumption than a typical Amba bus. It is aimed for uses across a wide array of communications, consumer or automotive designs.

SNAP supports up to eight cores on a layer and up to 16 layers on a chip. It can handle data rates up to 266 MHz in a 90 nm process.

The tool, now in a beta release, offers a graphical development environment. SNAP will be in general release in July and available at a per seat licensing cost of about $100,000.