MANHASSET, N.Y. — Semiconductor Research Corp.'s (SRC) Focus Center Research Program and Carnegie Mellon University have developed simple design elements called "logic bricks" for use in IC design libraries.

Logic bricks exploit chip design methodologies and how IC patterns are best printed using lithography tools. The approach allows use of existing lithography and manufacturing processes, enabling further advances that would otherwise be problematic for chip designers, according to the university researchers.

The new design elements rely on simplified design rules and regular patterning. The technology has been validated at the 65- and 45-nm nodes, and is being tested at the 32-nm node.

"This will help us to maintain the needed balance between smarter and affordable architectures," Betsy Weitzman, executive director of SRC's's center, said in a statement.

The new technology could lead to simplified design flows, particularly reduced leakage with improved control across chip line-width variations.

CMU said it has designed an embedded processor and taped out several other blocks at 65 and 45 nm.

"They have demonstrated in silicon that design with logic bricks does not imply a cost or performance overhead." said Intel Fellow Shekhar Borkar.

Ongoing research into logic bricks has been spun out for commercialization by Fabbrix Inc.. Fabbrix was acquired by PDF Solutions in order to make the new approach available to the IC design-for-manufacturing market.

The research "has demonstrated that communicating through a small number of predictably composable logic elements, or logic bricks, rather than conventional design rules, creates the bandwidth required to make such co-optimization possible," said Lars Liebmann, distinguished engineer with IBM's Semiconductor Research and Development Center.

IBM and PDF Solutions recently announced an agreement to leverage IBM's chip design and process development technology with PDF Solutions' pdBRIX IC design product. The pdBRIX technology uses similar logic bricks, and will initially be used to develop a set of templates to assist designers in creating design intellectual property at the 32-nm node.