Severe oversupply has resulted in steep price drops in 2008, forcing the swift retirement of 8-inch DRAM capacity and pushing forward to the 12-inch capacity in order to lower the DRAM production costs by major manufacturers. In 2009 it is widely expected that most manufacturers will migrate from 60- and 70-nm devices to more advanced 50-nm devices.

Samsung and Hynix, two of the industry's DRAM leaders, have already begun migrating their production of major products to the 50-nm class process node. Latest analysis on both 1-Gbit DDR2 SDRAM parts from Samsung and Hynix revealed very interesting trends from the two Korean rivals.

The two 1-Gbit DDR2 SDRAM devices that Semiconductor Insights (SI) has analyzed (shown in Figure 1) are from the 50-nm class process node. The analysis confirmed that the process node of the Samsung device is 58 nm; SI confirmed this by measuring multiple wordline and bitline pitches using cross sections obtained via a scanning electron microscope (SEM). The same measurement techniques were used to determine the process node of the Hynix device as 54nm.

Samsung 1Gbit DDR2 SDRAM

Despite the larger wordline and bitline pitch, Samsung's DRAM cell achieved smaller cell size by using a 6F²-based cell design. On the other hand, Hynix's 8F² cell design showed a 16.5 percent larger cell than Samsung's. It should be noted, that despite the larger cell size, Hynix's 1-Gbit DDR2 SDRAM achieved an impressive chip size of 45.1 mm², only 2.7 percent larger than Samsung's 1-Gbit DDR2 SDRAM. The floorplans for both devices look very similar; one exception includes Samsung design having two rows of pads in the central region; whereas, the Hynix design has all the pads aligned in one row.

In terms of DRAM cell and access transistor structure, the two rivals show very different approaches. As for Samsung's 58-nm process technology, the cell design appears to have been changed from S-RCAT (spherical-shaped recessed channel access transistor) to RCAT. It appears that the tight pitch of 6F² cell design poses a challenge to design an S-RCAT-based cell. The Hynix's 54-nm process technology maintains the same 8F²-based S-RCAT structure for the cell and the access transistor. To compensate for the change from S-RCAT to RCAT, Samsung appears to have made the RCAT recess deeper than that of Hynix's.

Another significant difference is the number of metal layers contained in Samsung's device. The Samsung 58-nm 1-Gbit DDR2 SDRAM device used only three levels of metallization, metal 1 is tungsten, whereas the remaining two metal layers are aluminum based. This is a significant change given that Samsung managed to achieve a very competitive chip size with only three metal layers. Previous generations of DDR2 products from Samsung used four layers of metalization. Given the importance of cost reduction in the DRAM industry, combined with the recent steep decline in DRAM prices, Samsung's 58-nm process technology with three metal layers is expected to achieve much needed production cost reduction, helping Samsung remain competitive in these tough market conditions.