A year or two ago, it looked like statistical timing analysis might be the next great new thing in IC design. Now it's less clear--and a debate at the recent International Symposium on Physical Design (ISPD) has brought some of the challenges into focus.

I was not able to attend ISPD, in Austin, Texas, March 19 to 21. But I received e-mails about the debate that took place over statistical timing and design. My information comes from ISPD 2007 program chair David Pan, professor at the University of Texas at Austin.

In a special ISPD 2007 session, Pan reported, prominent researchers from Intel and IBM painted different pictures of statistical timing and design. Noel Menezes, who directs Intel's Strategic CAD Lab, gave a talk titled, "The Good, the Bad and the Statistical." He showed the most recent results from an Intel study in which global statistical techniques have been applied for statistical timing analysis, skew computation, yield prediction, and joint performance-leakage modeling. Menezes' conclusion: the returns of fine-grained statistical analysis techniques are small compared with an "intelligent corner selection approach."

Rather than trying to look at timing variations over a selection of best- and worst-case temperature, process or voltage "corners," statistical timing analysis returns statistical distributions. The big problem with corner analysis below 65 nm is that there are too many corners, and, thus, too many separate runs for conventional static timing analyzers. But if there are better ways to select the corners, perhaps the advantage of statistical timing analysis is reduced.

The second speaker in the special session was Chandu Visweswariah of IBM Research, a well-known advocate of statistical timing analysis. In a talk titled "Fear, Uncertainty and Statistics," Visweswariah said that hardware performance is a distribution, and that die-to-die variations are critical. A single metric is not enough. Visweswariah proposed a phased adoption of statistical optimization, ranging from deterministic optimization with manual fix-ups to a truly distribution-based optimization.

Lou Scheffer, Cadence Design Systems fellow, commented that the two points of view are "three sides of the same coin." Scheffer said there are three effects that cause problems with the traditional static timing analyzers--correlation, sensitivities and statistics. Statistical timing has historically considered all three, and regular static timing analysis has ignored all three.

But there are other possibilities, Scheffer said. You could have, for example, a deterministic static timing analysis with sensitivities and correlations.

"I think industry will try all means to control and reduce variations first, through process and intelligent design," said Pan. "Designers in general don't know how to deal with probability distributions. Thus, how to do more intelligent deterministic design is key, as shown by the Intel study. A truly statistical design methodology will take time to gain acceptance."

I think Pan has a good point. It seems clear that statistical timing analysis will give the most accurate picture of how a design will respond under various process conditions, telling designers, for example, what kind of yield they can expect at a given frequency. But who really needs it, and are there alternatives?

In an article published last month on the EDA DesignLine, authors from Sierra Design Automation argue that statistical timing analysis is not a replacement for corner analysis. "Statistical analysis addresses one piece of the variability problem," the authors report. "It is useful for predicting circuit performance with a certain distribution. But hold violations still depend on analyzing and optimizing for the actual corner that causes the violations and leads to chip failure.

"So, the need to analyze and optimize a design for all possible process corners is not alleviated," the authors said. "Also, the availability of verifiable statistical device and interconnect models is very limited at the present time. Further, the challenge involved in getting the library vendor and designers to buy into statistical analysis cannot be underestimated."

Others have noted that statistical timing analysis is mainly useful for random process variations. Systematic process variations can be modeled, observers say, and should be removed from the statistical analysis. Systematic variations include lithography effects, most interconnect variations including lithography and chemical-metal polishing (CMP) effects, and most voltage and temperature variations. They're the greatest part of the problem, many say.

Another problem with statistical timing analysis is coming up with the statistical models to drive the analysis. The first problem is that foundries are hesitant to disclose statistical data. The second is generating the libraries in the first place. According to library characterization startup Altos Design Automation, statistical models can take 20 to 50 times longer to characterize than static models, and those already take too long. That's because statistical models track variations over multiple parameters.

Altos claims to have a solution, and if the company's technology works as advertised, it will greatly aid the adoption of statistical analysis. However, another problem is the lack of a standard library format for statistical analysis. As of now, each statistical tool has its own format. The Silicon Integration Initiative's Open Modeling Coalition (OMC) is working to forge a standard.

There was a debate about statistical timing analysis at last year's Design Automation Conference, where Synopsys announced a statistical timing capability so quietly it almost went unnoticed. Dennis Buss, vice president for silicon technology development at Texas Instruments, said that about the only thing that's truly statistical are random dopant fluctuations. With anything else, statistical timing may give the wrong answer, Buss said.

Philippe Magarshack, vice president of central CAD at STMicroelectronics, argued on behalf of statistical timing: "In real life, I believe we can't accurately predict temperature and voltage variations. We may have to take a statistical approach to compensate for these unknowns."

In conclusion, I'd say that statistical timing analysis is a promising technology whose time has not come. But it will eventually, and, meanwhile, traditional static timing analysis must change.

Richard Goering is software (EDA and embedded development tools) editor for EE Times. Contact him at rgoering @cmp.com.