Headlines and summaries from the pages of Electronic Engineering Times . Previous editions are available from the 1994 , 1995 , 1996 , 1997 , and 1998 News Archives.

04/19/96

OEMs skirt ATM spec freeze by backing Cornell U. project

From NAB: C-Cube rolls third-generation MPEG-2 encoder

Environmental regs increase demand for chemical sensors

IC designers say EDA industry unready for submicron era

Eagle tool enables 'pins-out' validation
What's new(s) at EE Times-interactive

04/18/96

VRML 2.0 draft spec out

Rules rewritten for engineering careers

Shift to systems-on-silicon is key to Motorola re-org

Fastparts Inc. brings electronic parts trading to the Web

Security Dynamics to acquire RSA

04/17/96

Philips rejuvenates itself with complex PLDs

Fujitsu tweaks ATM 4 x 4 s witching chip

Unitrode spins terminator for UltraSCSI

Filler improves package thermal properties

Learning system includes feedback control loop

National offers GTL+ termination voltage for Pentium Pro

04/16/96

Multiplayer games scheduled to hit the Net by late Spring

MIT proposes 10 giga-ops/second reconfigurable processor

SGI extends NFS to accelerate data in networked apps

Aldec, Cypress, beef up VHDL synthesis tools

04/15/96

Clash between PC industry, Hollywood, threatens launch of DVD

Intel designing 3-D chip as entry to peripheral controller business

Intel eschews VLIW design for 64-bit Merced (a.k.a. the P7)

Roadmaps that can tell "You are here" coming from Siemens

Legislators push to halt space station cooperation with Russia

Europeans define digital-TV silicon

EDAC, USEDA hold elections

OEMs skirt ATM spec freeze by backing Cornell U. project

By Loring Wirbel

ITHACA, N.Y. -- Even as the ATM Forum met in Anchorage voted this week on a 12-to-18-month "spec freeze" on new standards, developers were cheering a Cornell University effort to transport asynchronous transfer mode cells inside Ethernet frames.

In fact, Cornell's Cells-in-Frames (CIF) project has turned into an alliance that has attracted OEMs and semiconductor vendors from both LAN and WAN environments, including 3Com, IBM, Microsoft Corp. and Sun Microsystems Inc. The group has vowed to work outside the purview of the ATM Forum, at least at first.

At its second meeting, in mid-April in Burlingame, Calif., the alliance made plans for several technology demos. It is keenly awaiting ASICs for a new breed of "attachment device" from ConnectWare Inc.'s ATM Systems Division (Foster City, Calif.). The devices, which are similar to a work-group ATM switch, would convert ATM cells in the backbone to Ethernet frames at the desktop. Other vendors are working on physical-layer silicon.

Because CIF in theory entails no new client hardware and less software overhead than LAN emulation and other schemes, vendors who got wind of it over the last six months began clamoring for a CIF Alliance. Other members include AMD, Fujitsu Microelectronics, Integrated Device Technology, Integrated Telecom Technology, Madge Networks, Nortel and Novell.

From NAB: C-Cube rolls third-generation MPEG-2 encoder

By Junko Yoshida

LAS VEG AS -- Trying to keep one step ahead of its competitors, C-Cube Microsystems Inc. is rolling out a third-generation MPEG-2 encoder chip set tailored to handle a broad range of complex encoding needs. It comes in three versions with seven, five or two chips for the broadcast, video-storage and authoring markets, respectively.

Based on the San Jose, Calif., company's newest VideoRISC Processor engine, the third-generation VRP3, the products halve the number of chips required for MPEG-2 encoding, C-Cube said. Late last month, IBM Microelectronics and LSI Logic Corp. each unveiled its first complete MPEG-2 encoder chip sets. The IBM solution uses three chips and the LSI encoder five chips.

A number of encoder system developers have committed to using the new chip sets, including Comcast Labs, DigiMedia Vision (formerly NTL Advanced Products Division), DiviCom, Scientific-Atlanta and TV/COM.

The core of the VRP3, the latest spin of C-Cube's multipurpose video-compression engine, comprises two 32-b it processors based on a proprietary RISC engine. The pipelined processors operate at speeds up to 60 MHz.

Environmental regs increase demand for chemical sensors

By Craig Matsumoto

ANAHEIM, Calif. -- The widespread acceptance of sensors and micromachining technology has spawned vendor forays into new markets, as evidenced by the activity at this week's Sensors Expo, here.

Motorola Inc.'s sensor products division (Phoenix) unveiled a chemical sensor designed for carbon-monoxide detectors. Motorola is also working on a chemical sensor tailored to detect multiple compounds.

The efforts build on the widespread use of chemical sensors in cars to help control vehicle emissions. As environmental requirements get more precise, the need for measurements--and sensors--increases.

Ironically, government rules are slowing down other potential sensor markets. "There's been a lot of emphasis on medical sensing or environmental sensing. The trouble is, with medical sensing you have to go through the FDA. It takes a lot of time," said Kish Goswami, who heads sensor research for fiber-optics company Physical Optics Corp. (Torrance, Calif.). Some environmental products as well rely on government approval that's left the technology "stagnating," he said.

IC designers say EDA industry unready for submicron era

By Nicolas Mokhoff

RESTON, Va. -- IC physical-design problems that pundits four years ago proclaimed "solved" brought some 120 experts back to the table here this week to address them anew. The fifth Physical Design Workshop, sponsored by the Association for Computing Machinery's Special Interest Group on Design Automation, explored the chasm between circuit layout and circuit functions in the deep-submicron realm and concluded that a lack of focus, not tools, is what's holding the EDA industry back from closing the gap.

"The CAD-research community is solving yesterday's problems rather than tomorrow's," said Cadence Design Systems fellow Lou Scheffer, a veteran floor-planning- and place-and-route-research specialist who spent two years as an IC designer.

Physical interconnect delay will overtake gate delay as a design concern by the year 2000, mandating a shift in the physical design flow for deep-submicron, said Thomas Yin, vice president of the research group at workshop cosponsor Avant! Corp.

Manfred Wiesel, a design manager at Intel Corp.'s microprocessor group (Hillsboro, Ore.), "The focus of EDA has been on ASICs, and the result is that creative tools have not kept up with submicron processes, increased clock speeds and electrical rules in today's full-custom designs," Wiesel said.

Eagle tool enables 'pins-out' valida tion

By Richard Goering

BEAVERTON, Ore. -- Introducing a new concept in ASIC verification, Eagle Design Automation has released EagleV. Targeted at hardware designers, the tool set lets users validate software models of ASICs along with diagnostics running in a software debugging environment. EagleV aims to solve the problem of "pins-out" validation by ensuring an ASIC will work within a larger system.

The company last year announced Eaglei, a hardware/software co-

simulation environment that allows software designers to debug applications code before the target hardware is constructed. EagleV builds on that by providing a different feature set aimed at ASIC designers.

"What's lacking in ASIC validation is a connection to the software," said Geoff Bunza, vice president for engineering at Eagle. "The tools and techniques available today don't recognize that ASICs are put together with a team."

Though people attempt pins-out validation with board-level simulation, Bu nza noted that they rarely have all the models that are necessary and that board-level logic simulation doesn't offer a connection to a software debugging environment. Logic emulation lets users run software on an emulated IC, but not until there's a gate-level net-list, Bunza said. EagleV, in contrast, can work at a behavioral, register-transfer (RTL) or gate level.

VRML 2.0 draft spec out

By Brian Santo

MOUNTAIN VIEW, Calif. -- Like a shot from a starter's pistol, the VRML Architecture Group's release of the first draft specification of VRML 2.0 Tuesday set developers on a sprint to create browsers, authoring tools and applications that will bring interactive 3-D to the Internet.

The release of the draft also starts something of a bandwagon race, between the proponents of VRML 2.0 and Microsoft Corp., which has released an alternative called ActiveVRML, as they try t o attract adherents to their respective standards.

The 2.0 version of the Virtual Reality Modeling Language (VRML) is based on the Moving Worlds proposal put together by Silicon Graphics Inc., Sony and Worldmaker. Several other companies contributed to the effort, which is spearheaded by SGI.

Though Moving Worlds will become the official VRML 2.0 standard, Microsoft will complicate the situation by aggressively marketing ActiveVRML as a de facto standard. The race is on to win over content developers.

Rules rewritten for engineering careers

By Robert Bellinger

MINNEAPOLIS -- If engineers had any doubts that the career rules have changed, those were erased at the IEEE-USA Ninth Biennial Careers Conference here.

Industry executives, engineering-career consultants and academics sounded a warning that the old rules--steady promotions, a 30-year career at one company, even a "job" as the profession has traditionally defined it--don't apply to a global, fast-moving economy.

In his keynote address, Honeywell chairman and chief executive officer Michael Bonsignore described the changes in the context of the much-transformed Honeywell. "Traditionally, functionality has been the engineer's primary domain. We have not always considered it the engineer's role to consider Honeywell's or the customers' business issues.

"Whether we could sell the solution to anyone else . . . scale up the manufacturing, or make a profit on it was someone else's worry."

Today, said Bonsignore, "customer orientation and managing the relationship are recognized as major components of an engineer's job."

He contradicted some career experts' contention that promotions have largely fallen by the wayside with the "flattening" of organizations. Though the advancement path has changed, he said, "we've shortened the cycle time for management development as we've increased the speed of everything else. As a side effect" of flattening, "it's easier to spot talent."

Shift to systems-on-silicon is key to Motorola re-org

By Martin Gold

PHOENIX -- The shift from conventional IC building blocks to core-based, system-on-silicon chips for consumer- and communications-system design was a key factor in Motorola's recent restructuring of its $8.5 billion Semiconductor Products Sector.

"Our customers are asking for very highly integrated solutions. We have to react," Fred Shlapak, general manager of Motorola's newly formed Communications and Advanced Consumer Technologies Group, said in describing the rationale behind the restructuring. Shlapak made the comments during an interview here this month at the Powered-By-Motorola conference, which honors the Motorola sector's key accounts.

The Motorola move coincides with the formation of application-s pecific organizations by an increasing number of competitors in the United States, Europe and the Far East.Texas Instruments Inc. (Dallas), for example, crafted a wireless communications unit last year from pieces of its digital signal processing (DSP), analog and mixed-signal operations.

"Our organization had been too fragmented," Shlapak said. "The structure consisting of many individual business units did serve our purpose for many years. But no longer can four independent divisions present their capabilities and products to a customer that wants a fully integrated solution. It has to come from one guy with an integrated message."

Fastparts Inc. brings electronic parts trading to the Web

By Terry Costlow

ELMHURST, Ill. -- A trading-company startup is tapping the World Wide Web as the vehicle to allow companies to buy and sell electronic parts. Fastparts Inc. contends that its Internet transactions will occur faster than the current brokering method and will provide more equitable prices to boot.

The Internet trading site will formally begin operating April 25, when a major auction of parts is held in conjunction with the Silicon Valley National Association of Purchasing Managers. The on-line auction will be held at the company's Web site: http://www.fastparts.com .

Fastparts is beginning with a charter membership of 28 contract assemblers, all drawn from the IPC, which is the trade association for board producers.

The goal of the trading company is to help these manufacturers and others find parts they need quickly or to rid themselves of inventories that can't be returned.

Security Dynamics to acquire RSA

By Loring Wirbel

CAMBRIDGE, Mass. -- Security Dynamics Technologies Inc. has offered 4 million shares of common stock to acquire RSA Data Security Inc. (Redwood City, Calif.). RSA has agreed to the deal, subject to shareholder approval.

RSA's stock price jumped from about $49 to over $60 since the announcement, increasing the value of the deal to over a quarter of a million dollars. Security Dynamics' stock rose more than 13 points, to $62.75, when the announcement of the offer was made last Monday. Founded in 1982 by public-key researchers Ron Rivest, Adi Shamir and Len Adleman, RSA had revenues of $11.7 million last year, with net earnings of still less than $1 million.

RSA, a developer of several popular algorithms and software development products for public-key cryptosystems, would operate as a wholly owned subsidiary of Security Dynamics and continue to be based in Redwood City. Jim Bidzos would remain RSA's president, reporting to Security Dynamics chief executive Charles Stuckey.

Philips rejuvenates itself with complex PLDs

By Ron Wilson

ALBUQUERQUE, N. M. -- Back when it was called Signetics, Philips Semiconductors was a powerhouse of sorts in the programmable logic business. But the company gradually slipped from a mainstream producer to a specialist in barely understandable state-machine parts, and finally slid off the screen. Now the company is changing all that, with a family of complex PLDs that delivers a startling combination of competitive speed and low power consumption--not alternately but simultaneously.

The Philips XPLA family looks from the block diagram like just about any other cluster-of-PALs CPLD. In this case, logic blocks that would be 36V16 PALs are grouped around a central interconnect matrix. All signals coming into the chip go through the central matrix for routing, and all outputs from the logic blocks go to the matrix as well as to external pins. The matrix is a partially populated switch, which Phili ps claims to be nearly inexhaustible in its routing capabilities.

The interesting features of the XPLA family start to appear at the next level down. Ordinarily, the logic blocks in a CPLD look pretty much like the inside of a 22V10 PAL. The Philips approach is entirely different. The 36 inputs to the logic block flow into an AND array. But they also flow into a PLA-array--an array with completely programmable OR-terms. Each of the 16 outputs can come from either the AND array or the PLA. This arrangement gives you almost complete flexibility in expanding, sharing or steering P-terms.

Fujitsu tweaks ATM 4 x 4 switching chip

SAN JOSE, Calif. -- Fujitsu Microelectronics Inc. has updated its 4 x 4 asynchronous-transfer-mode (ATM) switching-element chip to accommodate new standards under development at the ATM Forum. The MB86681 SRE-L device moves the CMOS process to a 3.3-V co re (with 5-V I/O), cutting power dissipation to allow smaller systems to support 155-Mbit/second switching rates for full-featured ATM customer premises equipment.

Barry Marsh, director of enterprise products at Fujitsu, said it was more important for the company to expand buffer size in its switch and to add early packet discard (EPD) support to the cell-handling matrix than it was to move to slower ATM interfaces, such as 25 Mbits/s. Though Fujitsu was a founding member of the Desktop25 Alliance for low-speed ATM, "155 Mbits now looks like the entry level for enterprise ATM," Marsh said.

Output buffers on the device have been expanded to 146-cell capacity, which can be divided into 121-cell low-priority 25-cell high-priority queues. A single bit in the routine tag assigns cell priority. Flow control of ATM cells has been enhanced with a cell-loss-priority bit, which determines when a cell should be discarded if the "fill" level of an output queue exceeds a threshold. A vertical-serial feature pr ovides specific flow-control information on each output queue.

Unitrode spins terminator for UltraSCSI

By Terry Costlow

MERRIMACK, N.H. -- Unitrode Corp. has unveiled a SCSI terminator with a 2-pF capacitance to suit the requirements of the faster, UltraSCSI version of the venerable interface.

Terminator designers have been working more closely with interface-IC makers to meet the demands of the 40- and 80-Mbyte upgrades to SCSI. Unitrode's 18-line UCC5618 is among the first to be designed specifically for the latest SCSI incarnation.

The design underscores the continued attention that SCSI-subsystem designers have paid to the termination issue. While termination has become much less of a problem in recent years, it's again rearing its troublesome head as engineers shift to UltraSCSI.

"Termination is very important for UltraSCSI," said Dal Allan, president of ENDL Consulting and secretary of the Small Form Factor Committee, which helped develop the UltraSCSI document. "It's got very high speed, and with SCSI, the faster you go, the worse it gets."

That's because the interface uses the reflections that bounce back on a line to add current. While some of that reflection is needed to boost the signal, too much will cause false signals, creating errors.

Filler improves package thermal properties

By Ashok Bindra

CHANDLER, Ariz. -- Amkor Electronics is developing a line of packages based on a thermally conductive filler from Dow Chemical Co. (Midland, Mich.) that replaces fused silica. Amkor uses Dow's silica-coated aluminum nitride (Scan) as a filler in semiconductor-molding compounds to improve thermal properties--a boost that translates into a reduction in the package's thermal resistance.

Dow is readying a variety of filler-grade aluminum-nitride (AlN) products and is developing fillers for liquid encapsulants and for die-attach adhesive and flip-chip underfill.

According to Amkor, the devices packaged in the Scan-filled molding compound could be available by the fourth quarter. The company intends to qualify the thermally enhanced packages by the third quarter.

Learning system includes feedback control loop

By R. Colin Johnson

WILMINGTON, Del. -- The learning capabilities of conventional neural networks mimic one component of human perception but fall far short of modeling the full process, according to proponents of a new learning model being refined here at E.I du Pont de Nemours & Co. Inc. Visiting scientist Ilya Rybak and his colleagues base their work on the notion that "everything humans do--learning, cognition, perception, recognition, etc."--is dependent on the p erformance of certain active behaviors in a certain order.

Rybak's team explains its behavioral theory of perception in a demonstration program that can be downloaded free over the Internet http://www.voicenet.com/~rybak/bmv.zip . The original work was conducted at the Lab for Neural Network Modeling in Vision Research at Rostov State University (Rostov-on-Don, Russia).

Neural networks model the learning capability of human brain cells to varying degrees, but seldom are the behavioral aspects of learning included. For instance, the critical features we look for in recognizing a face have much to do with the type of processing that follows. Actively scanning features in a given order is a critical function that must be included in learning algorithms if they are to mimic human perception realistically, Rybak asserts.

Nationa l offers GTL+ termination voltage for Pentium Pro

By Ron Wilson

SANTA CLARA, Calif. -- Gunning Transceiver Logic received quite a kick last year when Intel announced its Pentium Pro CPU would use a variant of the much-debated GTL+ spec for its external bus. Suddenly, companies that design personal-computer motherboards needed to work with the unfamiliar levels and tiny voltage swings of this emerging standard.

While designers have scrambled to find ASIC vendors that offer GTL+ I/O, they have had a more obscure problem to solve. GTL and GTL+ both require a center termination to an intermediate voltage--1.2 V for GTL and 1.5 V for GTL+. To achieve necessary noise margins, that voltage has to be maintained very precisely. And across a 64-bit bus, the reference can be called on to source a good deal of current. Therefore, designers need to come up with a 1-percent, low-voltage reference with several amps of capacity.

To that end, National Semiconductor offers a shunt regulator chip , which, placed in a suitable feedback loop, will provide the regulated termination voltage these standards require.

The LM3460 packs a compensated op amp, a 1.22-V bandgap, a resistive divider and an npn output transistor into a five-lead SOT23. The part offers 1-percent regulation at 25ýC, and 2 percent over the full operating temperature range.

Multiplayer games scheduled to hit the Net by late Spring

By Junko Yoshida

SANTA CLARA, Calif. -- Internet service, system and application providers are getting serious about a frivolous pastime: multiparticipant, interactive game playing over the Net.

At the recent Computer Game Developers Conference (CGDC), service providers--claiming to have addressed the latency and bandwidth problems that have kept interactive games off the public network--shared technical white papers, sponsored workshops and ran demos of network-ba sed games. The first multiplayer-computer-game services on the Internet are due to arrive this spring and summer.

Among the providers that announced services were Dwango (Houston), Mpath Interactive Inc. (Cupertino, Calif. ), Total Entertainment Network (TEN, San Francisco), Imagination Network (Burlingame, Calif.) and Catapult Entertainment Inc. (Cupertino, Calif.). Some offerings will emphasize low latency for fast action; others will support real-time two-way voice conversations, multiplayer chat areas or other opportunities for social interaction.

Microsoft Corp. added to the momentum by announcing its DirectPlay Internet Gaming Architecture, a part of the DirectX API set that will support multiplayer gaming across any network.

MIT proposes 10 giga-ops/second reconfigurable processor

By Chappell Brown

HONOLULU -- A reconfigurable processor design that could exec ute 10 giga-operations/second on a chip is being proposed here this week at the 4th annual conference on FPGA Custom Computing Machines. Devised by the MIT group that created the dynamically programmable gate-array (DPGA) architecture, the Matrix approach uses reconfigurable interconnect to link 8-bit processing elements in a programmable "byte-slice" architecture.

While the arrangement reintroduces some fixed processor elements--such as registers and arithmetic logic units (ALUs)--into FPGA design, the overall architecture is highly reconfigurable. That allows the programmer, rather than the chip architect, to target processor resources for a given problem.

Indeed, the researchers said, Matrix can directly implement a spectrum of parallel-processing architectures, from highly regular pipeline and systolic arrays to more flexible, multiple-instruction, multiple-data (MIMD) and very long-instruction-word (VLIW) approaches.

"We don't view this as a departure from the DPGA philosophy," said pro ject leader Andre DeHon. "Rather, it addresses some of the issues that are difficult to tackle with a fine-grained approach."

SGI extends NFS to accelerate data in networked apps

By Loring Wirbel

MOUNTAIN VIEW, Calif. -- While other Network File System server vendors try to beat out Sun Microsystems Inc.'s NFS server performance through operating system kernel or utility improvements, Silicon Graphics Inc. has elected to make its own extensions to NFS to improve parallel channel performance in networked applications.

SGI this month is introducing Big Data Service (BDS) extensions to NFS, a move the company said will speed data throughput 10 to 20 times over high-speed channels such as the High Performance Parallel Interface (HiPPI). The protocols can coordinate packets in up to four HiPPI channels operating at 50 Mbytes/second each, for an aggregate data throughput of 200 Mbytes/s. Though first implementations were in HiPPI, network systems engineering manager Art Beckman emphasized that BDS could work with any physical channel above 100 Mbits/s, including Fiber Channel, OC-12 Sonet/ATM or 1000 Base T (Gigabit Ethernet).

SGI already had added features to all its Irix workstations and servers to create the NFS-based file system called XFS. Jay Kidd, director of network product marketing, said that "XFS allows BDS to become relevant," since XFS's 400- to 500-Mbyte file system for reads allows BDS to take advantage of fast I/O subsystems. BDS can be implemented on single-CPU systems, but shows better performance improvements in the larger symmetric multiprocessing systems, like the Challenge series, that are SGI's forte.

Aldec, Cypress, beef up VHDL synthesis tools

By Richard Goering

BOSTON -- Two vendors have made significant VHDL synthesis announcements on the eve of next week's PLDCon '96 show here. Aldec Inc. (Henderson, Nev.) has added VHDL synthesis to its Windows-based tool suite, while Cypress Semiconductor (San Jose, Calif.) has beefed up the synthesis offering in its $99 Warp2 product.

For Aldec, VHDL synthesis is a natural addition to an existing product line. The company's Active-CAD products tightly link schematics with gate-level simulation, and Aldec recently rolled out an HDL editor and a state-machine editor. OEM versions of Aldec's schematic, simulation and HDL editing tools are part of the new Foundation series tools from Xilinx.

Aldec's Active-Synthesis product uses VHDL synthesis technology from Metamor (Beaverton, Ore.), which also resells its VHDL compiler through Xilinx and Synario Design Automation (Redmond, Wash.). The synthesis capability currently supports only Xilinx, but promises support for Actel, Altera and Lattice by the end of June.

Cypress Semiconductor, unlike Xilinx and Aldec, developed its own synthesis technology in-house. Warp2 release 4 promises big gains in VHDL synthesis compared with previous versions, especially for pASIC 380 FPGAs. Norman Taffe, product marketing manager at Cypress, said the company's new UltraGen synthesis technology offers a 30 percent improvement in CPLD area and performance, and a three-to-four fold improvement with FPGAs.

Clash between PC industry, Hollywood, threatens launch of DVD

By Junko Yoshida

SAN JOSE, Calif. -- The PC industry fired back last week in the battle over DVD copyright protection, issuing a "list of critiques" of the technical specifications proposed by Hollywood and the consumer-electronics industry. The clash, if it continues, could derail the scheduled 1996 launch of the digital video disk.

"No way will we simply accept it as is," said Alan Bell, project manager of storage systems and technology at the resea rch division of IBM's Almaden Research Center. He confirmed that the list was formulated during a meeting here last week of the Technical Working Group (TWG) of the computer industry.

TWG's concerns range from a high-level policy issue--whether the currently unregulated PC industry should accept a government-regulated copyright system as proposed by Hollywood --to a low-level, technical issue of whether the device driver in a DVD-ROM drive is the right place to recognize the copy-generation management system encoded in a DVD.

Intel designing 3-D chip as entry to peripheral controller business

By Ron Wilson

FOLSOM, Calif. -- Despite its long-standing policy of avoiding the peripheral controller business, Intel Corp. is quietly designing a 3-D graphics accelerator chip here, EE Times has learned. The device, which will use the recently unveiled Accelerated Graphics Port, is i ntended as both a prod to the third-party graphics chip industry and another new product area for Intel.

Intel would make no comment about the project. But industry sources stated last week that a joint design with an outside contractor--believed to be Lockheed-Martin Microelectronics--has been under way for some time and is close to an announcement.

According to these sources, the new chip will use a different partitioning scheme than most of the current generation of 3-D accelerators to double or triple system-level 3-D performance.

Intel has several motivations for developing its own 3-D accelerator. One is simply to follow the model of its wildly successful core logic business. In core logic, the company has used detailed knowledge about processor and PCI characteristics, plus a virtual lock on the high-end PC motherboard market, to become the single dominant supplier of Pentium core logic chip sets.

But another, possibly deeper, motivation is to direct the evolution of 3-D graphic s technology. This is because 3-D, with its boundless computing loads, poses a threat to Intel's ability to deliver adequate system performance. Simply put, with 3-D accelerators moving in the direction they are today, Intel will not be able to make CPUs run fast enough to keep up with rising demands for 3-D performance.

Intel eschews VLIW design for 64-bit Merced (a.k.a. the P7)

By Alexander Wolfe

SANTA CLARA, Calif. -- Intel's upcoming Merced--the 64-bit microprocessor that's being jointly developed with Hewlett-Packard behind tightly closed doors--won't be a very-long-instruction-word (VLIW) design, but will be a heavily modified superscalar architecture that exploits instruction-level parallelism and pushes the envelope of instruction pre-decoding technology, according to experts close to the effort.

Although Merced, formerly known as P7, isn't expected to see the light of day until 1998, when it will see initial service in 64-bit Unix servers aimed at high-powered Internet and enterprise applications, a more thorough picture of the chip is now coming together. According to experts in the know, four clear data points have emerged:

1. Merced won't be a classic VLIW architecture, but it will decode instructions into a series of primitive "micro-operations" and schedule multiple micro-op streams for simultaneous execution. Merced will take this technique--which is already used in the Pentium Pro--to new levels of complexity. The overall design goal is to take advantage of instruction-level-parallelism as much as possible.

2. The processor will make extensive use of instruction pre-decoding and tagging, to attempt to create a correspondence between micro-op streams and the chip's functional units. The implementation, while not VLIW, will be something of a spiritual cousin of that technology.

3. Merced will incorporate on-chip decoders for object-code compatibi lity. One decoder will convert x86 instructions into Merced micro-operations. A second may be added to convert HP-PA instructions; however, it's more likely that the PA code will be handled by software translation.

4. New compiler and operating-system technology will be developed specifically for Merced, with the goal of extracting maximum performance from its 64-bit architecture.

Roadmaps that can tell "You are here" coming from Siemens

By R. Colin Johnson

PRINCETON, N.J. -- Is the end in sight for that insistent nagging hassle plaguing every weary traveler--namely, determining just where you are on the map? Within two years, neural technology now emerging here from Siemens Corp. Research Inc. promises to put a red blinking dot, indicating "You Are Here," on maps for automotive, industrial and even handheld applications.

The key to the technology is a neural learning method that solves the automatic vehicle locator (AVL) problem. "Human perception is very complex--not even a Cray can perform human-like perception--but most aspects of perception are not used for navigation. If all you want to do is navigate, then you can get away with something that runs in real time even on slow computers," said Siemens' project manager, Stephen Judd.

Siemens' AVL technology first learns a street map from video tapes of driving on those streets. Thereafter, the trained neural network recognizes the previously learned "sensory signatures" of landmark locations and displays the corresponding map, complete with blinking red "You Are Here" dot.

Siemens' AVL works by using a unique combination of neural, expert system and traditional technologies. Visual input data is gathered with a conventional video camera that is pointed straight up into a reflective sphere yielding a 360-degree panoramic view.

Software then analyzes the scene to remove moving objects and other "noise" before landmarks are extracted, their sensory signatures learned and stored on a CD-ROM. At run time a neural network in the field compares the learned landmarks on CD-ROM to the real-time ones coming in from a moving video camera. The identified landmarks in the database are then linked to the street-map database, enabling the display of "You Are Here."

Legislators push to halt space station cooperation with Russia

By Loring Wirbel

COLORADO SPRINGS, Colo. -- Key members of the House of Representatives are ready to hold NASA's feet to the fire to halt international space station efforts in favor of a possible revamped version of the U.S.-only space station Freedom.

Rep. James Sensenbrenner, chairman of the space and aeronautics subcommittee of the House Science Committee, told the 12th Annual Space Symposium here that he wanted the White House to prepare a contingency pla n by June to end collaboration with Russia on the space station.

The reason: Russian budget crises are calling into question future critical launches of space station components. Plans call for the station to be built in more than 40 steps between late 1997 and mid-2002, primarily by the U.S. and Russia, with some European Space Agency involvement. The first core power component developed in Russia, the Functional Energy Block, looks certain to make a November 1997 launch date, but delays appear to be serious in the Russian Service Module scheduled for an April 1998 launch.

"The problem is not with RSA," said Sensenbrenner, referring to the Russian Space Agency. "The problem is not with Khrunichev or Energiya [two privatized rocket-manufacturing facilities]. The problem lies in the Russian government's failure to fund operations of its facilities."

Europeans define digital-TV silicon

GRENOBLE, France -- A group of 11 European companies and institutions, led by chip maker SGS-Thomson Microelectronics, has started development on a chip set for digital-terrestrial-TV receivers. The two-year initiative, called DVBIRD, for digital video broadcasting integrated receiver decoder, is part of the European Commission's Advanced Communications Technologies and Services (ACTS) R&D program.

In its first phase, the program will define the architecture for a first-generation chip set, leading to production of demonstrator equipment. In its second phase, DVBIRD will define a second-generation chip set optimized for all three forms of digital-TV delivery: cable, satellite and terrestrial radio. The European Digital Video Broadcast (DVB) has standards covering all three delivery systems. They're all based on MPEG-2 data compression and decompression .

The U.K. and Spain are expected to introduce digital-terrestrial-TV services in the next year or two.

EDAC, USEDA hold elections

San Jose, Calif. -- The Electronic Design Automation Companies (EDAC) last week announced a restructuring and elected a new board. Meanwhile, the User Society for Electronic Design Automation (USEDA), which was spawned by EDAC, is seeking nominations for its own election.

Following a model established by the Semiconductor Industry Association, EDAC has created a nine-member board consisting only of CEOs and COOs of voting member companies. The board includes chief executives from Aptix, Cadence, Design Acceleration, Engineering DataXpress, High-Level Design Systems, Mentor, Orcad, Synopsys and Viewlogic.

Mentor president Wally Rhines was elected EDAC chairman. The two vice-chairmen are Viewlogic president Alain Hanover and Synopsys president Aart de Geus.

USEDA is seeking nominations for president, vice president, secretary and treasurer through April 26. Ballots will then be distributed and election results announced at this year's Design Automation Conference. Nominations should be e-mailed to useda-bod@netcom.com .

Free Subscription to EE Times First Name Last Name Company Name Title Email address   Click here for your Free Subscription to EETimes Europe