EET-i Top of the News
Week of 12/25/95
- 12/28/95
 Pact paves way for U.S. digital radio
- Viewlogic buys Silerity
- Davic seeks modem spec
- Japan pushes jump to 12-inch silicon wafers
- Shortage of polysilicon, 8-inch wafers looms
What's new(s) at EE Times-interactive
- 12/27/95
- All-CMOS imaging challenges CCDs
- Nefclass neural networks offer explicit learning
- Neural simulator harnesses multiprocessors
- 12/26/95
- Cascade eases IC migration with library development tools
- Mitel chips handle N. American, Euro line interface speeds
- Low power to the coax people
- 12/25/95
- Merry Christmas!
 Pact paves way for U.S. digital radio
ARLINGTON, Va. -- The final obstacle to testing of a U.S. digital audio radio system has been removed with the resolution of an interference dispute, an industry sponsor said.
The Electronics Industries Association (EIA) filed an amendment on Dec. 15 to its application for an experimental license that includes an agreement specifying a test protocol with detailed frequency coordination procedures to avoid interference with aircraft testing during digital radio field tests. The agreement with the National Telecommunications and Information Administration (which oversees spectrum issues for the Commerce Department) and the Aerospace & Flight Test Radio Coordinating Council is expected to clear the way for Federal Communications Commission approv
al of an experimental license.
Field testing of Eureka 147, one of seven proposed digital audio radio systems, is expected to begin in San Francisco in February using L-band frequencies (1,452 to 1,492 MHz).
EIA's Digital Audio Radio Subcommittee and a broadcasters group plan to present their test results to the FCC by midyear.
Earlier disputes over testing procedures threatened to delay field tests.
Viewlogic buys Silerity
By Richard Goering
MARLBORO, Mass. -- In a new assault on the ASIC-synthesis marketplace, Viewlogic Systems Inc. has acquired Silerity (Pasadena, Calif.), a startup founded by Carver Mead and David Johannsen. When Will Herman, then Silerity president, returned to Viewlogic as chief operating officer early last year, the company said it would buy Silerity.
Viewlogic paid about $5.6 million in cash and payments contingent on future sales. Johannsen and
Richard Doherty, another Silerity founder, are now Viewlogic employees in the High Level Design group. Mead, a professor at the California Institute of Technology, will serve on Viewlogic's technical advisory board.
Last June Silerity introduced PathBlazer for data path optimization. A supplement to existing synthesis tools, it optimizes data paths at a high level of abstraction, using process-specific topology information. Production-quantity shipments are expected in the third quarter.
Davic seeks modem spec
By George Leopold
WASHINGTON -- With work complete on set-top and interactive-TV standards, the Digital Audio Visual Council (Davic) is shifting gears to tackle cable modem standards. The group wants to nail down modem and other new specs by June in conjunction with a cable-industry effort.
Davic completed its first interoperability framework in Berlin on Dec. 16. After
final editing, copies of the Davic 1.0 specification will be released to the group's 205 member companies in mid-January. The spec sets global standards for a range of digital interactive services and will be updated frequently.
But Davic members said the rise of the Internet during their year of deliberations has prompted them to make high-speed cable modems one of the group's highest priorities over the next six months. Leading cable and equipment companies announced a similar effort in November to be headed by CableLabs (search our archive for story on Dec. 4, 1995, page 1).
Davic spokesman Robert Luff, chief technical officer for Scientific-Atlanta Inc.'s Broadband Communications unit, said the group will work with CableLabs to forge cable-modem standards for high-speed Internet access and other interactive applications. "We all want one system, not two or three," Luff said.
Japan pushes
jump to 12-inch silicon wafers
By David Lammers
TOKYO -- A handful of Japanese IC manufacturers this year will lay the groundwork for the shift to 300-mm (12-inch) wafers, a move that will more than double the dice yield per wafer. But doubts persist that the wafer-manufacturing industry, already capacity-strained on the current, 200-mm (8-inch) generation, will be able to turn out sufficient quantities of the larger wafers to satisfy commercial requirements.
NEC Corp., for one, is undaunted. Senior vice president Yuichi Haneta said the company is building a pilot line for test production of 1-Gbit DRAMs on 12-inch wafers. The $500 million Sagamihara ULSI Center will begin processing in 1997, using e-beam and excimer laser lithography to fabricate 1-Gbit DRAMs in a 0.18-micron process.
"My target is to begin commercial production in 1998 or 1999 with 300-mm wafers for 256-Mbit DRAMs," Haneta said. His boss, NEC executive vice president Hajime Sasaki, claimed to be "more conservative.
My target is not 1998, but 1999, and even that depends on having space at NEC Kyushu at that time."
Motorola Inc. has stuck by its announced plans to use the larger wafers for microprocessor fabrication by mid-1998. And at the Semicon Japan show last month, Applied Materials executives showed a chart claiming that seven IC makers will begin using 300-mm wafers for production within 1998. Though none of the companies was identified by name, four were identified as Japan-based.
Shortage of polysilicon, 8-inch wafers looms
By David Lammers and Yoshiko Hara
TOKYO -- A shortage of bulk polysilicon and finished 200-mm (8-inch) wafers is almost certain to worsen over the next few years, as the rapid growth of the IC fabrication industry outpaces the supply-side increase from the polysilicon and wafer producers.
Semiconductor-materials industry analysts Dan Rose, president of Rose Asso
ciates (Los Altos, Calif.), and Clark Fuhs, of Dataquest Inc. (San Jose, Calif.), both have weighed in with reports that detail a wafer supply-demand mismatch that will extend through the rest of the decade.
However, Jim Glaze, vice president of technology at the Semiconductor Industry Association, questioned whether the shortage scenarios are too linear, i.e., failing to sufficiently take into account the ability of the industry to adapt.
Other sources said as many as half of the 8-inch wafers are now being used as "dummy" wafers for testing new equipment and process lines. If the industry could cut back on the number of test wafers, the shortages could be less severe than predicted.
"We are now experiencing the fastest wafer-production ramp-up in silicon history, with over 80 new 200-mm wafer fabs expected to be entering production by the end of 1997," said Rose, who has been following the vagaries of the wafer industry for 25 years. "But wafer manufacturers have not yet mastered the technology
of producing 200-mm slices in high volumes with optimum yield."
All-CMOS imaging challenges CCDs
By Chappell Brown
PASADENA, Calif. -- Charge-coupled device (CCD) technology has long held a comfortable niche as a low-noise imaging architecture that has stayed ahead of the price curve of competing approaches. But that entrenched position is increasingly threatened by an all-CMOS imaging technology. Called active pixel sensors (APS), the devices promise to take electronic imaging to price/performance levels that could someday leave CCDs in the dust.
Eric Fossum, who presented a road map for APS at last month's IEDM conference, is so confident of the technology's promise that he's forming a startup to commercialize an APS approach he has been developing at the Jet Propulsion Laboratory. "Active-pixel-sensor technology is highly appropriate as a next-generation camera technology," F
ossum said. "By integrating camera functions with a light-sensing operation, APS offers far more functionality than CCD technology and could lead to a rugged, low-power camera on a chip."
While CCDs enjoyed brief popularity as a specialized memory type for early VLSI generations, integration and scalability issues soon forced the devices out of the running. But the technology has long been widely valued for its utility in imaging applications. When operating purely as an image sensor, CCD chips offer superior low-noise performance and can be manufactured in standard silicon processes.
A single CCD is essentially a MOS transistor, yet, despite its simple architecture and good noise performance, CCD technology has some inherent disadvantages that won't improve much with scaling. The charge-transfer operation requires particularly high voltages, leading to high power consumption, and the analog output signal requires A/D conversion chips. And because of their dimensions, CCDs cannot be integrated with st
andard CMOS VLSI circuits to achieve the scaling and on-chip processing advantages of standard IC technology.
That is precisely where such newer schemes as APS derive their leverage.
Nefclass neural networks offer explicit learning
By R. Colin Johnson
BRAUNSCHWEIG, Germany -- Combining the learning ability of neural networks with the if-then rule creation of fuzzy logic, Nefclass (NEuro-Fuzzy CLASSification) sports the advantages of learning without the disadvantages of neural networks. The software package is offered by researchers Detlef Nauck and Rudolf Kruse at the Technical University of Braunschweig and may be freely used for educational, scientific or personal purposes.
Nefclass attacks a fundamental problem of neural learning: After a neural network has learned a set of synaptic weights for a problem, its solution is incomprehensible to the trainer. With Nefclass, on
the other hand, its trained weights can be linguistically interpreted as fuzzy rules, such as "If the temperature is very hot, then turn on the air conditioner." Also unlike neural networks, which must be initialized with a random set of weights, Nefclass can be initialized with a premade set of if-then rules-of-thumb, which learning then fine-tunes.
"The advantage of incorporating fuzzy logic into our neural-network model is the interpretation of its internal structure in the form of linguistic rules, some of which can be specified ahead of time," said Nauck. "For instance, sometimes simple rules for extreme cases are known in advance, such as 'If all values are small, then it's class X.' "
Nefclass fuzzifies the traditional perceptron-style neural network by learning fuzzy rules directly from raw data. The supervised learning method uses a fuzzy version of back-propagation-of-errors. After training, Nefclass classifies patterns into crisp sets.
Neural simulator harnesses multiprocessors
By R. Colin Johnson
ERLANGEN, Germany -- Erlangen University has translated into English its NeuroGraph simulation environment for neural networks, which features plug-in support for fuzzy logic and genetic algorithms. Unlike monolithic simulators, NeuroGraph was designed from the bottom-up for multiprocessing by using separate independent modules for all functions. Both its data structures and function libraries support parallel execution on multiple processors using either message-based or shared-memory communications schemes.
"The most unique feature of NeuroGraph is its multiprocessing support," said Stuart Bar-On, president of the Parallel Performance Group, which is marketing a commercial version of NeuroGraph in the United States. "If you have access to other workstations on your network, for instance, you can really accelerate neural learning and other time-consuming tasks by running
them on several processors simultaneously."
Both the learning step during system development and the later pattern-recognition steps of a finished application can be run in parallel on distributed nets of uniprocessors using message-passing, or on a local multiprocessor. Alternatively, finished applications can be compiled into standard C programs for sequential execution on most platforms.
Cascade eases IC migration with library development tools
By Richard Goering
BELLEVUE, Wash. -- Leveraging its silicon-compilation technology, Cascade Design Automation has introduced MasterPort, the first in a series of IC library-development tools. MasterPort lets IC vendors migrate physical cell libraries from one process technology to another.
Cascade is aggressively targeting the relatively small library-development niche because of a compelling need for automation, said Ken Rousseau, vi
ce president for new product development. "The way people have been doing library development to date is starting to break down," he said. "They need a way to collapse the library-development cycle in order to meet time-to-market."
Rosseau said it typically takes six to nine months--and perhaps five to 10 man-years of effort--to develop or migrate an IC cell library today. He claimed that with MasterPort, a customer was able to migrate a library to a new, deep-submicron process within a few weeks, saving "an order of magnitude" in time.
Mitel chips handle N. American, Euro line interface speeds
KANATA, Ontario -- Mitel Semiconductor has introduced three devices that meet primary-rate ISDN interface rates for North American T3 speeds (45 Mbits/second) and European E3 speeds (38 Mbits/s).
While leased E3/T3 lines have been slow to grow, the interest in providing primary-rate ISDN circu
it services over the T3/E3 infrastructure has accelerated the need for standard silicon, said product manager Mel Roberts.
The three new members are the MT90732 E2/E3 multimode framer, the MT90737 multiplexer/demultiplexer and the MT90733 multimode framer for both fractional T3 and digital cross-connect.
Line terminals
The 732 is intended for line terminals, in wideband data or video-transport applications and in multiplexers. It can interface to systems using NRZ or dual-rail signals, performing all framing functions for E2/E3 line rates per International Telecommunication Union specs.
Low power to the coax people
TUSTIN, Calif. -- While the bulk of attention may be on twisted-pair LAN, Silicon Systems Inc. is out to prove to the coaxial cable world that power-consumption advances are being made for 10 Base 2 and 10 Base 5 transceivers. The 78Q8392L device draws 50 mA when trans
mitting and 7 mA for line monitoring while receiving data.
The new transceiver is a BiCMOS redesign of a custom transceiver SSI developed for Standard Microsystems Corp. Kirk Brinkworth, network product marketing manager at SSI, said that the company decided to move to a low-power BiCMOS version after observing "a huge remaining market for coaxial adapter cards in the U.S., Europe and the Far East. People keep predicting the decline of coaxial cable but pushing out the date for that decline."
Since the BiCMOS device has such a low current drain compared with bipolar or CMOS parts, SSI has made a special effort to work with dc/dc converter makers, including parent TDK, to develop a 500-mW power converter to use with the transceiver. Joint marketing efforts to promote such devices will allow PCs with a coaxial Ethernet interface to meet low-power specs such as EPA's EnergyStar.
Merry Christmas!
Happy holidays from the staff of EE Times.
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