EET-i Top of the News
Week of September 11, 1995
- September 14, 1995
 TI spins DSP for videoconferencing
- Cryoelectronic PCS field test completed
- Lattice PLD breaks 5-ns wall
- Harris pumps DSSS LANs
- 3Soft gets Passport to Compass libraries
- Talk to Jaron Lanier, live on CompuServe!
What's new(s) at EE Times-interactive
- September 13, 1995
- Faltering 3DO tries new game
- Job market still has little room for layed-off engineers
- Joint 'biochip' project eyes artificial retina
- Manufacturers prepare for ISO 14000
- September 12, 1995
- LAN switches to be highlighted at Networld+Interop
- MEMS sensors look to drive automobiles
- Core logic speeds embedded-RISC CPUs
- Motorola's hot Coldfire aimed at middle ground
- Board sports 64-bit CPU
- Accel buffs up P-CAD
- Data-acquisition card plugs into PCI slot
- September 11, 1995
- Intel's VTUNE makes Appendix H unnecessary
- Fujitsu ups magneto-optic drive capacity
- Microsoft moves to capitalize on Windows 95 beachhead
- Wanted: new I/O scheme for 120-MHz-plus DRAM arrays
- Atmel to broaden its line of complex PLDs
- Teradyne grabs Megatest
- Price parity seen on 3-, 5-V DRAMs
- Supercomputer will use P6 CPU
- Three IEEE re-org models shot down, but fourth in the works
Other news sources on Techweb:
TI spins DSP for videoconferencing
By
Ashok Bindra
HOUSTON --Texas Instruments Inc. is working with third-party software developers on bundled videoconferencing solutions based on the TMS320C82, the newest member of the TMS320C8X family of multiprocessor DSPs. A Peripheral Component Interconnect-based reference design for implementing the H.320 and H.324 videoconferencing standards using the C82 digital signal processor is slated for mid-1996 delivery, with the complete solution expected to debut early in 1997.
TI unveiled the C82 recently at a unit price of $82 in lots of 25,000, positioning the part as a low-cost single-
chip replacement for dedicated videoconferencing chip sets (see July 31, page 1). Integrating two 32-bit fixed-point DSPs (the C80 has four) and a pared-down, 44-kbyte SRAM, the chip is slated to sample in the second quarter of '96 and hit volume production in the second half.
The planned videoconferencing solution will bundle hardware and software into one package for desktop PCs, said Rick Rinehart, multimedia-DSP program manager for TI's Semiconductor Group. He said TI is confident that the C82's 1.5 billion operation-per-second (Bops) performance and $82 price tag will make the part a volume driver in the videoconferencing market.
Cryoelectronic PCS field test completed
SAN DIEGO -- Telecommunications-IC vendor Qualcomm Inc. said this week that it and Superconducting Core Technologies Inc. (SCT) have completed the first field test of a cryoelectronic personal communications services (
PCS) base-station receiver front end.
The tests were performed using Qualcomm's Code Division Multiple Access (CDMA) 2-GHz PCS test system here. The companies said that successful implementation of cryoelectronic technology could achieve advances over the current high level of CDMA system performance by enabling CDMA PCS base stations to receive weaker signals that would otherwise go undetected.
Higher system performance would allow carriers to further reduce costs, since even fewer cell sites would be required, Qualcomm officials said.
SCT's cryoelectronic receiver front end used high-temperature superconducting narrowband, multipole filters and cryogenically cooled low-noise amplifiers to improve the selectivity and to lower the noise figure of both RF channels in a Qualcomm CDMA base-station receiver. The test results indicated that SCT's equipment produced a 6-dB improvement in the noise figure. That improvement could reduce the number of base stations required for a PCS operator to deploy by as
much as 50 percent, Qualcomm said.
Lattice PLD breaks 5-ns wall
By
Ron Wilson
HILLSBORO, Ore. -- Lattice Semiconductor Corp. will break through the 5-ns barrier on Monday with the announcement of its 3.5-ns, 3.3-V GAL16LV8D--the first member in a projected family of sub-5-ns small PLDs. The CMOS chip, significantly faster than any 5-V CMOS part or even the best bipolar PLDs, opens new applications for programmable logic. But it could also close a chapter in the story of TTL-compatible logic.
"The speed improvement is about two-thirds underlying technology and about one-third circuit design," claimed Lattice director of marketing Stan Kopec. "The part is built in a new 0.5-micron, 2-metal process, [called] UltraMOS VI."
Kopec said that Lattice was able to use thinner oxides in the low-voltage process, and to reduce some metal runs, both d
irectly boosting performance. Additional performance gains came from circuit tweaks, based on the work already done in Lattice's 5-ns, 5-V parts.
Kopec said to expect a 3.5-ns 22V10 chip within six months.
Harris pumps DSSS LANs
By
Loring Wirbel
MELBOURNE, Fla. -- Harris Semiconductor's wireless-applications strategy of digitizing functions in intermediate-frequency (IF) domains has yielded one of the most efficient chip sets to date for wireless LANs. In early October, the company will bring out a four-chip Prism set for implementing direct-sequence spread-spectrum (DSSS) wireless LANs in the FCC's unlicensed 2.4-GHz bands.
Harris worked closely with Advanced Micro Devices Inc. to ensure the chip set would interface directly with AMD's new wireless medium access controller (see Aug. 28, page 18). With slight revisions, however, Prism c
an also be used in such markets as wireless T1/E1 digital-line replacement and digital-cordless-phone service. Full-duplex modes allow the chip set to be used in continuous-bit-rate voice services as well as with data.
Nonetheless, Wes Kilgore, product-marketing manager for analog signal processing at Harris, said the vertical-market opportunities in wireless LANs may well swamp other applications for the first few months of the chip set's existence.
3Soft gets Passport to Compass libraries
By
Richard Goering
BRIGHTON, England -- A technology and marketing agreement between Compass Design Automation (San Jose, Calif.) and 3Soft Corp. (Santa Clara, Calif.), to be announced at next week's EuroDAC trade show here, will link Compass's Passport physical libraries to 3Soft's synthesizable macrocells. The three-year agreement calls for 3Soft to o
ptimize some of its more complex macrocells for implementation in Passport.
Separately, Compass is announcing formal support for the Passport library from European Silicon Structures (ES2). The support is for ES2's 0.6-micron, 3-V CMOS ASIC process.
While the 3Soft Macroware library is aimed at logic designers using synthesis tools, Passport libraries enable IC layout designers to use multiple foundries. The agreement "spans the bridge" between logical and physical design, according to Ken Brock, product line manager at Compass.
"Logic designers can very easily and quickly synthesize [3Soft] megacells down into a silicon-correlated library and have ICs manufactured at many different foundries," Brock said. "And they will be able to get size and performance estimates quite quickly."
Talk to Jaron Lanier, live on CompuServe!
On Wednesday, September 20, log on to CompuServe's Conferenc
e Center for an open discussion with Jaron Lanier, the virtual reality pioneer and cyber-pundit. Lanier is co-inventor of the DataGlove, and is credited with coining the term "Virtual Reality." Lanier will be on hand to comment on VR, the Web, Internet commerce, and his recent CD of music based on a variety of non-Western instruments.
This conference is sponsored by
EE Times
and its engineering forum on CompuServe, EEtnet.
Read the first two parts of a three-part interview with Lanier.
Part one
is about VR on the Web,
Part two
about commerce on the Internet.
Faltering 3DO tries new game
By
Junko Yoshida
REDWOOD CITY, Calif. -- Faltering as a new breed of consumer-electronics company, 3DO Co., started here three years ago, has decided to reinven
t itself. The new strategy: license pieces of its core 3-D graphics and full-motion-video technologies to PC chip, card and system vendors.
Instead of slugging it out in the cutthroat videogame market, the company now hopes to better control its own destiny. But the more important goal, said Hugh Martin, chief operating officer, is to "build up-front cash flow."
That road to riches is not exactly wide open. More than a dozen other companies in the Silicon Valley alone are already offering their own 3-D graphics and multimedia solutions in a competitive PC multimedia market.
And this time around, if the company fails to reach its goal, 3DO's managers will have nobody to blame but themselves. But at least they will have the benefit of hindsight at the company's much touted original business plan.
That scheme, designed to establish credibility and outside commitments for the startup, called for a set of very powerful investors and strategic partners ranging from the world's leading consumer electro
nics giant to content owners and network-system vendors. Among the gilt-edged chosen were Matsushita, AT&T, Time Warner, MCA and Electronic Arts.
Job market still has little room for layed-off engineers
By
Bob Bellinger
CEDAR RAPIDS, Iowa -- Nearly half (48 percent) of the IEEE members who reported being unemployed in late 1994 or early 1995 were still involuntarily jobless this August, according to an IEEE-USA Employment Assistance Committee survey released at the recent Professional Activities Committee for Engineers (Pace) conference and workshop.
Among the 888 respondents, some 20 percent of those who had reported being jobless a year ago have since found full-time jobs as engineers. Ten percent reported finding employment outside the profession, 7.5 percent reported being employed part-time, and another 7.5 percent said they w
ere self-employed.
Finding a new job was a tough task, members told the EAC committee. Some 85 percent said it was "very difficult to find a new job." And more than one-third said they are taking or expect to take a pay cut in a new position.
Most of the respondents blamed business downturns for their being let go. Just over half (55 percent) said the layoffs were targeted at specific units; the remainder said the layoffs were "across the board."
Joint 'biochip' project eyes artificial retina
By
R. Colin Johnson
CAMBRIDGE, Mass. -- A collaborative project between MIT and Harvard has raised the possibility that surgeons will one day be able to attach artificial retinas to the nerve nets of the human eye, restoring sight to those with retinal damage. The researchers say their project could demonstrate the world's first artificial retina
"in vitro" as early as next year.
"Interfacing to a real biological system is a very long and tedious process; it makes normal electrical engineering seem simple," said MIT professor John Wyatt. But Wyatt hopes to do just that in a system under joint development with Harvard medical doctor Joe Rizzo.
The most common cause of blindness is genetic or accidental retinal damage. In many such cases, the optic nerve and the ganglion cells feeding the retina remain intact and operable.
The research team has leveraged that fact along with a lucky accident of anatomy: In the human eye, the ganglion cells are located atop the retina, so that light passes through them before striking the retina. In other words, said Wyatt, "The ganglion cells are there right on the surface, where a biochip can easily get at them."
Manufacturers prepare for ISO 14000
By
M
argaret Ryan
NEW YORK -- It's not expected to be approved until mid-1996, but ISO 14000, an International Standards Organization (ISO) document directing manufacturers to establish environmental-management systems, already has electronics and computer companies evaluating their procedures with an eye toward compliance. Consultants and ISO registrars helping companies gear for the standard say 14000 registration will not come without cost--and, therefore, without some measure of controversy.
The draft standard covers setup of environmental-management systems, procedures for environmental audits and performance evaluations, and guidelines for environmental labeling and product-life-cycle assessments. The document has been under development since 1991 under the auspices of ISO--the same group, comprising more than 90 member countries, that drove the ISO 9000 quality-management standard to near ubiquity.
Since ISO 9000's adoption in 1992, certification to the standard, while voluntary, has effec
tively become a prerequisite for companies seeking to do business in Europe and Asia, and it is fast becoming a necessity in the United States as well. ISO 14000 is expected to travel much the same path to virtually universal acceptance.
LAN switches to be highlighted at Networld+Interop
By
Loring Wirbel
ATLANTA -- LAN switches will take center stage at next week's NetWorld+Interop where vendors will scope out differentiators for new architectures.
While most of the activity is in frame switching, where dedicated links are created between node and hub, LANart Corp. (Needham, Mass.) is out to prove that there are plenty of new ideas in the port-switching world. The company is promoting its SegWay port switch as the perfect feeder to enterprise-level frame switches.
Meanwhile, FDDI switching expert Network Peripherals Inc. (NPI; Milpitas,
Calif.) is adding Fast Ethernet to its repertoire. In addition to combining 10-Mbit frame switching with 100-Mbit repeater functions, NPI touts its SnapSwitch family as the only one to offer legitimate IP fragmentation on a per-port basis.
Two vendors are attempting opposite tacks to merge frame and Asynchronous Transfer Mode (ATM) cell switching. Fore Systems Inc. (Warrendale, Pa.) has repackaged the switch offered by its new subsidiary, the former Applied Network Technology Inc., and is offering the switch under the ForeView management system. Meanwhile, enterprise-frame-switching expert Alantec Inc. (San Jose, Calif.) is offering its first ATM modules in the PowerHub family and is showing off interoperability with Fore Systems switches.
MEMS sensors look to drive automobiles
ROSEMONT, Ill. -- Microelectromechanical systems, commonly called MEMS, have made only slight inroads into the dri
ving force for sensor technology--the huge automotive market. The prospects for greater acceptance, as well as for some of the technologies that will help MEMS, were among the hot topics at the Sensors Expo here this week.
Makers of MEMS sensors say that their solid-state products are desirable because they can let car makers meet longer warranty periods, help meet legal mandates and enhance vehicle diagnostics. Automotive designers are becoming more interested in solid-state technologies, such as sensors, to meet those goals. A survey of the market, presented by Roger H. Grace Associates (San Francisco), noted that 41 percent of the $27 billion MEMS market will go to the automotive industry.
Grace Associates predicts that sensors will be a key technology in active suspension systems, providing data that will enable a smoother ride. Antilock braking systems (ABS) are another application with potential.
Core logic speeds embedded-RISC CPUs
By
Ron Wilson
SAN JOSE, Calif. -- There has been a substantial increase in the amount of CPU horsepower that designers are throwing at their embedded-computing problems these days. A 32-bit embedded processor used to mean something similar to a 68020--now it can mean a RISC chip with a 64-bit bus and a 133-MHz clock rate. But while CPU speeds have skyrocketed, the performance of core logic for embedded processors hasn't necessarily kept pace. Often, designers may have to design their own core logic--a significant challenge in itself at these speeds. The alternative may be to use core logic from some previous design, which may be electrically compatible with the latest CPUs, but may not even come close to providing the memory or bus throughput the CPU needs.
Galileo Technology has addressed that issue for those using the Integrated Device Technology (IDT) R4600, R4650 and R4700 chips. These CPUs are fast--u
p to 150-MHz internal clock--MIPS R4000 processors with 64-bit system-bus interfaces. They are used primarily in applications that require a combination of high computing loads and very high-throughput rates.
Those very applications are the ones most sensitive to bottlenecks in core logic. If the actual memory bandwidth is a fraction of what the CPU needs, the whole system throughput will rest on the hit rate of the CPU primary caches. If the I/O bus--frequently these days a PCI bus--jams up under heavy traffic because of inadequate FIFO buffers or poorly thought-out state machines, the CPU will spend a good deal of its time waiting.
Motorola's hot Coldfire aimed at middle ground
By
Ron Wilson
AUSTIN, Texas -- Motorola Microprocessor and Memory Technologies Group continued the delicate job this week of trying to find room for a whole new fami
ly of 32-bit CPUs in between the ubiquitous but aging 68000 family and the new but untried PowerPC family. Positioning the 68000s as the most inexpensive, legacy-compatible group, and the PowerPC chips as the absolute high end, Motorola has a hazy middle ground available for its technically elegant Coldfire architecture.
Coldfire combines the best of two worlds in many ways. The instruction set is a proper subset of the 68020 set, leading to at least familiarity, and in many cases code compatibility, with the older 68000s. But the execution unit is a tiny five-stage pipeline that executes all of the instructions without resorting to microcode.
Using modern design ideas on an old--and trusted--instruction set yields impressive results. Motorola claims that Coldfire has a code density in between that of the 68040--possibly the most efficient embedded-computing engine ever mass-produced--and the original 68000. That makes it substantially better in terms of memory consumption than any purely RISC embedded
CPU.
Board sports 64-bit CPU
By David Lieberman
MADISON, Wis. -- Heurikon Corp. is first out of the chute with a CPU board based on Integrated Device Technology's 64-bit R4700 Orion MIPS processor. The Baja4700 VMEbus board, which will ship in October, features a 70-Mbyte/second, 64-bit VMEbus interface and is also the first board to be announced with a pair of Peripheral Component Interconnect mezzanine card (PMC) expansion sites on board.
A Heurikon ASIC is partially responsible for the Baja4700's high VMEbus throughput, according to vice president of engineering Dennis Terry. The part, described as a data-ordering gate array, provides a buffered link between the board's 32-bit local bus and its 64-bit VME-interface chip, Terry said.
The board sports several of the enhancements being developed for the bus by the VMEbus International Trade Association (VITA) standards organization. T
hose include geographical addressing and 35 additional ground lines.
Accel buffs up P-CAD
By
Richard Goering
SAN DIEGO -- Accel Technologies is reasserting its commitment to the P-CAD line by preparing a major enhancement to the Master Designer product. The new release, Version 8.5, adds such features as net attributes and will be available this fall under DOS and Unix.
Accel is also clarifying a product strategy that has taken shape since its abrupt purchase of P-CAD in January. "Master Designer will continue well into the future as we see it today," said Accel president Walt Foley. "We're following up on our plan by providing the enhancements and bug fixes we believe Master Designer users were looking for."
There will be another Master Designer release in mid-1996, Foley said. Meanwhile, Accel is working on a new line, under the code na
me Sequoia, that will combine Accel's TangoPro offering with P-CAD technology. The Sequoia product will be available under Windows in the first quarter.
Existing TangoPro users, along with P-CAD users who want to move to Windows, will be migrated to Sequoia. P-CAD users who want to stay with DOS or Unix will be able to purchase Master Designer for the foreseeable future.
Data-acquisition card plugs into PCI slot
By
Stan Runyon
MONTREAL -- The Gage Applied Sciences CompuScope 6012/PCI is a data-acquisition card set that plugs in to a PCI slot. That means data can be transferred at a rate of up to 90 Mbits/second, instead of the 2-Mbit/s limit of the ISA bus.
With that kind of throughput to the PC's memory, the analog-to-digital (A/D) card can be rearmed faster than ever, meaning engineers can design complex A/D converter systems with high p
ulse-repeat frequencies. Such systems find application in radar, lidar, sonar, medical imaging, non-destructive testing, laser velocimetry, and so on.
Alternatively, users can opt to build A/D-based systems with deep memories, going to relatively inexpensive DRAMs on the PC, rather than SRAMs. For example, storing 20 million samples of data in on-board SRAMs in an imaging application (a few frames worth of data) could easily cost over $20,000, according to Gage. With DRAMs, that cost drops to $3,000.
Intel's VTUNE makes Appendix H unnecessary
By
Alexander Wolfe
The saga of the Pentium performance-monitoring registers detailed in Intel's Appendix H is about to come to a close. The story reared its head earlier this summer, after German hacker Christian Ludloff reverse-engineered some of the information and posted it on the Internet. Perhaps spurr
ed by those leaks, Intel decided to make public its official documentation on the registers. The information is printed in the just-released updated edition of the three-volume Pentium User's Manual.
Now comes word that programmers won't have to burn the midnight oil deconstructing either Intel's documentation or Ludloff's hackings. That's because Intel is about to release its Visualized Tuning Tool (VTUNE), a software profiler that makes heavy use of the performance-monitoring registers to enable developers to see how their applications are executing on Pentium and other X86 processors.
"It profiles your code and allows you to graphically look at how your software is operating," said Richard Wirt, an Intel Fellow and the director of the company's microcomputer research labs. "We look at the entire system--all the low-level code in the operating system, as well as time spent in the application."
Fu
jitsu ups magneto-optic drive capacity
By
Yoshiko Hara
and
David Lammers
TOKYO -- When IBM Corp., the world's largest computer maker, announced it would no longer develop magneto-optical drives, the M-O storage business lost one of its key players and left the technology almost entirely up to No. 2 Fujitsu Ltd. and several other Japan-based companies.
Now researchers at Fujitsu Laboratories say they have developed a new M-O disk technology that can store up to 4 Gbytes of data on a double-sided disk, or 2 Gbytes on a single-sided 3.5-inch platter. The higher capacities derive from changes in the rewriteable disk itself, and not by pushing the laser technology from 680 nm to 650 nm wavelengths, said Shigeru Sato, president of Fujitsu Laboratories.
The 2-Gbyte and 4-Gbyte drives won't be ready until summer 1997, and the more complex disks will cost about 20 percent more than conventional M-O platters. But
at the upcoming Fall Comdex Show in Las Vegas, Fujitsu expects to have 640-Mbyte drives for desktops, and 17-mm-high notebook M-O drives that store 230 Mbytes.
As for IBM, a spokesman its Storage Systems Division will focus on hard disk drives and its high-end Magstar tape drives, abandoning low-end and mid-range tape and optical drive development.
-- Terry Costlow contributed to this story
Microsoft moves to capitalize on Windows 95 beachhead
By
Alexander Wolfe
REDMOND, Wash. -- Microsoft Corp. last week fired a series of technology salvos aimed at buttressing the beachhead it has established with Windows 95.
The software giant said it is ready to ship a developers' version of Direct-X, a set of software application-programming interfaces (APIs) for graphics and sound. Originally intended for games, Direct-X now appears destined
for a key role in multimedia, computer-telephony and other so-called host signal processing (previously known as Native Signal Processing) applications.
Separately, Microsoft joined with Intel last week to formally unveil release 1.0 of the Universal Serial Bus, a crucial enabling hardware element of the Plug-and-Play effort. The bus is expect to spark the development of a wave of external PC peripherals aimed at home users who have shunned add-in cards requiring complex configuration sequences.
And sources close to Microsoft report the company is quietly proceeding with plans to release quarterly Windows 95 "tune-up packs"--in effect, upgrades--for its new operating system. The upgrades will include technology that Microsoft omitted from the initial release of Windows 95, as it rushed to meet its promised August shipping date.
Taken together, the moves constitute a concerted effort to push the PC architecture to the next stage, by evolving the platform from a loosely related series of subsystems
into a far more unified collection of technology specifications encompassing communications, telephony, 3-D graphics and even games.
Wanted: new I/O scheme for 120-MHz-plus DRAM arrays
By
Ron Wilson
SAN MATEO, Calif. -- As samples of the second generation of synchronous DRAM (SDRAM) chips quietly become available, indications are that the memory and fast logic industries are locked on a collision course over logic levels. Virtually everyone agrees that a new, low-voltage swing I/O scheme will be needed for DRAM arrays operating at 120 MHz or more.
But each memory vendor seems bent on pushing its own version of a low-swing specification. JEDEC, having already standardized several incompatible specifications, appears to be slipping into the background in the controversy. And now programmable logic vendors are beginning to approach the speeds w
here they, too will have to adopt a new signaling spec. As each vendor becomes more entrenched in a particular approach, the possibility of a single interface standard for SDRAMs appears to be slipping away.
Atmel to broaden its line of complex PLDs
By
Brian Fuller
SAN JOSE, Calif. -- Atmel Corp. will broaden its complex programmable logic device (CPLD) line later this year, with an IC that targets 44-pin devices--perhaps the most lucrative segment of the CPLD market--EE Times has learned.
The specialty logic and memory vendor, which has methodically moved up the density scale from simple logic devices to CPLDs and FPGAs, will introduce the ATF1500 family as early as late next month, the company confirmed last week. Significantly, the device will be pin-compatible with Altera Corp.'s lucrative 7032 member of the Max 7000 family--a series that h
as no second source to date.
"The CPLD market is better and better defined with time," said Jim Fahey, Atmel's marketing director. "It's been a tremendous inconvenience for users to have to tolerate different pinouts for different devices. We're doing a standardization with the most popular devices."
While the 2500 was Atmel's first 44-pin CPLD device, the 1500 will be the first device with 32 macrocells, the company confirmed. In addition, it will be less expensive and be targeted at designs that don't need the power of the 2500, Fahey said.
Teradyne grabs Megatest
By
Stan Runyon
BOSTON -- Shock waves reverberated throughout the ATE industry late last week, as Teradyne Inc. announced it has agreed to acquire competitor Megatest Corp. (San Jose, Calif.), in a stock deal valued at $245 million.
Megatest will become a division of Teradyne
and will keep its name and location for the foreseeable future. Megatest chairman and CEO Jack Halter will become general manager of the division and a vice president at Teradyne.
Revenue did not seem to be a big factor in the merger. Teradyne is running at a $1 billion rate, while Megatest--which has struggled in recent years--has fought back to reach $150 million this year. In fact, Megatest just reported revenue of $38 million for the quarter ending in August, with a backlog exceeding $50 million.
Teradyne's motivations appear to be acquisition of missing technology and the opportunity to tap important markets that have proved elusive. Megatest, in turn, saw the need for a source of capital to fund new generations of ATE machines.
Price parity seen on 3-, 5-V DRAMs
SAN JOSE, Calif. -- Fujitsu Microelectronics Inc. (FMI) said last week it expects that, by early next year, it will be sell
ing 3.3-V DRAMs for the same price as the generally less-expensive 5-V parts.
George Robillard, FMI's director of memory business, said the move enables the company to scrap the traditional price premium for low-voltage memory that PC OEMs have to pay and eliminate the last 5-V part from the typical motherboard design.
The price premium for low-voltage parts generally has been 10 to 15 percent.
Fujitsu is ramping a 0.35-micron process at its 8-inch facility in Awate, Japan, and will do the same at Gresham, Ore. The company has tipped unofficial plans to build a third 8-inch 0.35-micron fab at Durham, England.
Supercomputer will use P6 CPU
SANTA CLARA, Calif. -- Intel Corp. last week was awarded a $45 million, multiyear Department of Energy contract to build a P6-based supercomputer that can deliver peak performance of 1.8 teraflops.
The machine is the first procurement under the Ener
gy Dept.'s Accelerated Strategic Computing Initiative (ASCI), a seven-year effort to secure supercomputing hardware and software powerful enough to simulate nuclear weapons (see June 19, page 1).
The massively parallel machine from Intel will have 9,000 CPUs and 262 Gbytes of system memory. It is scheduled for completion by the end of next year and will be built by Intel's Scalable Systems Division (SSD) in Beaverton, Ore.
The announcement marks the first admission by Intel of its P6 supercomputing plans. Though it had been widely assumed that Intel SSD was planning to use the P6 in massively parallel supercomputing, Intel had long declined to comment.
Three IEEE re-org models shot down, but fourth in the works
CEDAR RAPIDS, Iowa -- The three models for IEEE reorganization appear dead in the water.
Even before the IEEE-USA Pace (Professional Activities Committee for Engineers) Conferen
ce formally considered the proposals for shaking up the volunteer structure last week--the Federation, Matrix and Traditional models, as they were called--the plans already had started foundering, according to IEEE leaders. Reaction to the plans was swift and negative, especially from the American engineers who perceived all three proposals as diluting the U.S. profile in the international technical society.
Fernando Aldana, chairman of the Strategic Planning Committee, flew in from Spain to confirm to the Pace attendees that if he were to go before the IEEE board of directors today, none of the plans would meet approval.
However, reorganization of IEEE is not dead. A fourth, more "measured," plan is in the works that will produce "a minimum of dislocation," said Joel B. Snyder, vice president of professional activities and chairman of IEEE-USA.
No final version has yet been drawn up, but Snyder told the Pace engineers that he sees an IEEE divided into two basic "columns," or legs: a globally focus
ed technical column and a "non-technical," or geographic, arm. (There would also be an "operations" arm that groups standards, educational activities and other cross-functional activities).
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