EET-i Top of the News

Week of May 29, 1995

June 1, 1995

Joint IC-modeling effort under way at DOE

Fore buys LAN vendor Applied Network Technology

Cascade moves to ATM

Weitek into unified memory

Seagate joins in the shift to MR heads

Activist Cooley wins USE/DA presidency
What's new(s) at EE Times-interactive

May 31, 1995

Sun makes risky bet on the 'Net

AT&T Microelectronics to focus on DSPs, ASICs

Sensor market poised for growth

Newton opened to handwriting-recognition firms

Amorphous silicon shows promise

EIA's 'Seal' project hits wall

VR tools come to the Net

May 30, 1995

ASC puts new twist on superconductors

All systems go for sensor standard

Asians add IC auto-assembly

VGA-to-NTSC encoder chip developed

Chip set aids dual-processor servers

IC hopes to shine at the office

May 29, 1995

Cold Warriors look back on first sky spy

Sun hitches UltraSparc to Intel PCI bus

Sun MP link aims to boost workstations

Moto to rejuvenate DSP line to regain merchant dominance

National, Samsung, Toshiba push NAND flash into future

Sharp to establish U.S. research arm

Happy Memorial Day

Other news sources on Techweb:

• Interactive Age
• Information Week
• Electronic Buyer's News

Joint IC-modeling effort under way at DOE

By George Leopold

WASHINGTON -- A five-year, $100-million effort unveiled last year to develop next-generation simulation and modeling tools for the U.S. semiconductor industry is under way at three Department of Energy (DOE) labs.

The effort is part of a semiconductor initiative launched by the Clinton administration and industry groups last year to speed implementation of the industry's 15-year semiconductor technology road map. Under a cooperative research agreement between the national laboratories and Semiconductor Research Corp (SRC; Research Triangle Park, N.C.), the DOE has established a Center for Semiconductor Modeling and Simulation at Los Alamos National Laboratory (Los Alamos N.M.). Researchers from SRC's member companies also are working with Sandia and Lawrence Livermore national laboratories.

The agreement includes work in five major areas:

• Implementation of new adaptive algorithms needed to model complex, three-dimensional device structures and manufacturing processes.
• Development of a combined equipment/wafer simulator that will describe how surface topography is affected during deposition and etch processes.
• Improved simulation tools to predict electron behavior in semiconductors.
• Improved methods to predict failure in interconnects based on microscopic grain characteristics.
• Predictive codes for IC-manufacturing processes such as ion implantation and impurity diffusion.

Fore buys LAN vendor Applied Network Technology

By Loring Wirbel

WARRENDALE, Pa. -- Fore Systems Inc. this week augmented its Asynchronous Transfer Mode networking with LAN frame switching, by acquiring high-profile newcomer Applied Network Technology Inc. (ANT; Westford, Mass.). Not only was ANT's ANTSwitch the recipient of a "Best of Show" award at the Spring Networld+Interop in Las Vegas, but the company has also been the design power behind the Cascade Ethernet switch ASIC core used by LSI Logic Corp. and Newbridge Networks Inc., as well as a separate LAN switching ASIC used by CrossComm Corp.

Fore paid $26 million of its own common stock and $9 million in additional stock options for ANT, which will be run as an independent division of Fore, focusing on workgroup access.

Simultaneously, Fore announced that it had paid an undisclosed sum to acquire a small routing-software specialist in Washington. Robert Schiff, director of marketing for workgroup access at Fore, said that RainbowBridge Communications Inc. had experience in both Internet and N ovell NetWare protocol stacks. The small company also was one of the originators of the ATM Forum's P-NNI (Private Network Node Interface) software standard. The combined acquisitions of ANT and RainbowBridge will expand Fore's expertise to frame switching and distributed LAN packet routing as well as ATM, Schiff said.

Cascade moves to ATM

By Loring Wirbel

WESTFORD, Mass. -- Cascade Communications Corp. has migrated from frame-relay to Asynchronous Transfer Mode switching, using a four-plane ATM architecture that could move the company's switch into customer-premises applications as well as carrier services. The Cascade 500 is an "edge switch" positioned against platforms from the likes of General DataComm Corp. and Stratacom Inc., though Cascade will be touting the architecture's superiority in handling multiple Quality of Service guarantees through multiple internal ATM-switching fabrics.

Cascade has partnered in the past with vendors ranging from Cisco Systems Inc. in routing to WilTel Communications and GTE in public networking. But its B-STDX frame-relay switches have rarely found a place in customer-premises hardware. Desh Deshpande, executive vice president at Cascade, said that the company deliberately waited until the ATM Forum had finished more standards before defining an architecture that could be applied to a range of carrier, Internet-service-provider and customer-premises applications.

Weitek into unified memory

By Ron Wilson

SUNNYVALE, Calif. -- Graphics-accelerator pioneer Weitek Corp. set the industry on a new path this week, announcing sampling of the first combined graphics and core-logic chip set for unified-memory PCs. The set, which uses main memory for gr aphics frame-buffer space, marks a new direction for PC architecture.

Opti Inc. previously announced its intention to develop a unified-memory chip set, and a number of other graphics and core-logic suppliers are believed to be working on such a design.

Unified-memory architectures eliminate the separate, specialized frame buffer used in current PCs, instead placing the frame buffer in main memory. Drawing operations are then performed either by the CPU or by a hardware accelerator integrated into the system core logic. Screen refresh is performed by a specialized DMA controller that extracts pixels from main memory and sends them to the screen.

Seagate joins in the shift to MR heads

By Terry Costlow

SCOTTS VALLEY, Calif. -- Seagate Technology Inc. has joined the shift to magnetoresistive (MR) heads, using the new technology to boost i ts Barracuda line to 8 Gbytes. Seagate expects to use the new MR drive to gain a foothold in the nascent market for Fiber Channel drives.

All three members of the Barracuda line boast MR heads, partial response, maximum-likelihood read channels and a spin rate of 7,200 rpm. That lets Seagate put 4 Gbytes in an inch-high package and jam 8 Gbytes into a full-height drive, both offering access times of 8 milliseconds.

Though Seagate is a leader in the high end of the drive market, it lags in MR introductions behind Fujitsu, IBM and Quantum Corp., all of which have MR products with higher densities than conventional inductive thin-film heads. But IBM is the only one shipping significant quantities, so executives at Seagate and analysts both agree that the disk-drive giant is not late to market.

"Whenever you build a new drive line, you're managing risk. Until now, we felt we could do the drives we wanted without the risk of going to MR," said Dave Anderson, product planning manager in Seagate's high-per formance group. "We feel our decision not to bring MR out until now has been a good idea."

Activist Cooley wins USE/DA presidency

By Richard Goering

SAN JOSE, Calif. -- EDA consumer activist John Cooley, a consultant and founder of the independent E-Mail Synopsys Users Group (ESNUG), has become president of the User Society for Electronic Design Automation (USE/DA) following an uncontested election. The result places an outspoken industry gadfly at the helm of the only significant vendor-independent EDA user's organization.

USE/DA was founded, and continues to be funded, by the Electronic Design Automation Companies (EDAC)--a heritage that once drew criticism from Cooley, who said, "It appeared a lot like Chrysler forming labor unions along with hand-picking who the labor leaders would be."

In his campaign statement, Cooley said he want s USE/DA to focus on a small number of issues; serve as a voice for EDA users; be staffed by users and not vendor representatives; and take a balanced view on issues such as the VHDL vs. Verilog debate.

USE/DA has launched a major effort to survey users on business practices, with results to be presented at the upcoming Design Automation Conference.

Sun makes risky bet on the 'Net

By Michele Clarke

SAN FRANCISCO -- In a move that is at the same time aggressive and risky, Sun Microsystems Inc. has announced a broad strategy to commercialize the Internet.

The four-point plan includes tools to access, "publish" applications, guarantee security, and perform commercial transactions over virtual networks defined by special gateway servers that won't have an IP address (thus rendering them invisi ble to conventional network software and hackers).

The key technologies include an interpreted scripting language that will establish a live, continuous link between user nodes and now-static host-system Web pages; the addressless-security scheme; and public-key encryption of individual transactions.

But much of the strategy's success lies in the hands of the government: Commerce Department restrictions on the export of encryption technology could prevent the suite from enabling electronic commerce beyond the U.S. market.

Indeed, the primary issue delaying implementation of Internet commerce, according to a Yankee Group study, is security. Less than 5 percent of Web sites currently perform secure transactions, estimated Katherine Webster, manager of Sun's Internet market development.

Sun chairman and CEO Scott McNealy added that Sun plans to offer a full set of services, including installation and maintenance at customer sites, to go with the tools. "We've been quietly running the Internet for q uite some time," he said. "Now we're planning to make some noise about it." Indeed, Sun machines represent more than 50 percent of an estimated 3.2 million Internet nodes, according to market analysts at International Data Corp.

The market potential of the business thrust is significant. Market researchers at Network Wizard estimate the number of Internet domains (e.g., sun.com, whitehouse.gov or mit.edu) at some 71,000. The group also estimates that 70 percent of Internet hosts are in North America, with 21 percent in Western Europe, 7 percent in Asia/Pacific, and 2 percent elsewhere (including Eastern Europe).

AT&T Microelectronics to focus on DSPs, ASICs

By Martin Gold

BERKELEY HEIGHTS, N.J. -- After nearly 10 years of slugging it out to expand share in the merchant semiconductor market, AT&T Microelectronics is streamlining its product focus.

The unit is discontinuing or selling off product lines (including the Hobbit processor), and plans to focus on developing and maintaining a leadership position in digital signal processing and in application-specific ICs. Areas of focus in the new business strategy also include certain carefully selected types of optoelectronic components such as chip sets for fiber optics, printed-circuit boards and backplanes, as well as some power-supply systems. With this portfolio, close to 50 percent of AT&T Microelectronics' estimated $2.6 billion in revenues this year will come from external OEMs; the balance still comes from other business units of AT&T.

"We made a lot of mistakes; we had to undo many things that we were doing," said Curtis J. Crawford, president of AT&T Microelectronics, referring to his task in recent years of penetrating the external OEM marketplace. In a wide-ranging interview where he spelled out the failures and successes of his operation, Crawford said: "We were in a lot of product businesses because of the historical perspective that we had to supply all of the needs of the corporation. But, to go forward, we concluded that there are alternatives for sourcing the corporation that didn't have to come from us."

Crawford's strategy is to stay with product lines in which his unit can hold either first or second place in market share.

Sensor market poised for growth

By Terry Costlow

BOSTON -- After years of failed predictions that solid-state sensors were ready to soar, that market segment's time may finally be at hand.

Vendors, sensing a surge coming in what's been a steadily growing market, point to technological innovations that have eased sensor integration. In addition, prices are dropping. Those two trends make it much easier for engineers to justify the use of this semiconductor tec hnology.

Much of the current takeoff is being driven by the automotive market. After a couple years of examination, car designers have started using accelerometers and other sensors to help determine when airbags should be set off.

"Accelerometers are a key area in the automotive industry, they're really starting to take off," said Jim Doscher, Accelerometer Marketing Manager at Analog Devices (Wilmington, Mass.). "This will be a big year. Automakers have used multipoint ball and tube sensors for airbags. This year will be the first year they are substituting solid-state sensors for those electromechanical systems."

Newton opened to handwriting-recognition firms

By R. Colin Johnson

CUPERTINO, Calif. -- Apple Computer Inc. will soon offer an applications-programming interface (API) for its Newton MessagePad system to rival pen-compu ting companies, and will unveil a homegrown handwriting recognizer that it will license to other vendors. The moves respond to complaints that the proprietary MessagePad technology effectively locked independent handwriting recognizers out of the Newton market.

The first customer for Apple's new handwriting-recognition API will be Lexicus Corp. (Palo Alto, Calif.). "We are working with Lexicus to create a new API that will enable it to bring its neural-network-based handwriting-recognition system to Newton," said Sandy Benett, director of software engineering for the Newton MessagePad. Once that task is completed, Benett promised, Apple will make the handwriting-recognition API generally available to any vendor that wants to use it.

Amorphous silicon shows promise

By Chappell Brown

TAIWAN -- Performance normally associated with the most de manding semiconductor materials systems is being coaxed from amorphous silicon in a project at National Cheng Kung University's VLSI Laboratory. By laying down thin layers of doped silicon, a double barrier containing a quantum well can be created. By carefully adjusting the thickness of these layers, the researchers were able to generate a pronounced resonant-tunneling condition that usually only occurs in refined superlattice structures.

The effect is used to build transistors that perform multiple functions, but so far, the route to practical devices has required compound semiconductor systems such as gallium arsenide and indium phosphide. Even with such advanced materials systems, room-temperature resonant tunneling is difficult to obtain.

While resonant tunneling has been found in amorphous silicon, the effect was not pronounced enough to be of practical use. The current breakthrough was preceded by work with a silicon/silicon carbide system. The wider bandgap of silicon carbide, and the advantage of a heterostructure interface produced devices with good peak-to-valley ratios in the negative differential region created by resonant tunneling.

EIA's 'Seal' project hits wall

By Robert Bellinger

WASHINGTON -- Legal issues and corporate objections have slowed an industry effort to establish a Seal of Accessibility that would cue buyers as to whether a product's design meets accessibility guidelines. Some consumers have specific accessibility needs -- for larger screens, or easy-to-turn dials, for example; the idea of the seal was to notify these consumers that a given product would accomodate them.

"We have a rough outline of the guidelines," said Jeanne Chircop, a staff director at the Electronic Industries Association. "An expert is reviewing them."

She denied that development of the seal has been "shelved," as some disabilit y advocates maintain. "It's still alive," she said.

However, at least one source close to the Seal of Accessibility committee at the Electronic Industries Association claimed that some consumer-electronics manufacturers have gotten cold feet over meeting guidelines.

For now, the proposal remains just that: a proposal. No timetable has been projected to bring the project to a conclusion, Chircop said.

"It's very complicated. It got more complicated the further we got into it."

VR tools come to the Net

By R. Colin Johnson

SAN JOSE, Calif. -- For a finale, VRWorld '95 poured forth a virtual waterfall of software tools for viewing virtual reality (VR) over the Internet. While most announcements at the recent conference centered on the virtual-reality modeling language (VRML), in which most of the new 3-D worlds are being created, othe r higher-end alternatives were offered, too.

Silicon Graphics Inc. (SGI; Mountain View, Calif.) demonstrated the first-ever family of VRML-based viewers, called WebSpace, designed in cooperation with Template Graphics Software Inc. The viewers can be freely downloaded off the Internet from: http://www.sgi.com/ Products/WebFORCE/WebSpace/.

Other vendors, however, promised support for creating virtual realities using VRML that would convey their content in 3-D, rather than merely serving as a fancy index to the normal 2-D multimedia pages. Caligari Corp. (Mountain View, Calif.), for instance, promised to deliver a VRML-based development tool, called the 3-D World Builder, modeled on its high-end "trueSpace2" software with animation, elaborate texturizing and photorealistic rendering.

Separately, Virtual Presence Ltd. (London) described its new tool, G Web, which offers all the capabilities of its high-end Genesis World Builder, including realtime processing of input sensors. G Web will import world m odels created in almost any 3-D modeling tool, and integrate them into a VRML-based Web page.

The first alternative viewer to WebSpace was announced, too. WebView, from VREAM Inc. (Chicago), acts as a "helper" application to any normal Web browser, kicking in only when the VRML is embedded in the normal HTML stream from a Web site. WebView has the added capability of enabling users to browse virtual realities created with either VRML or in the high-end VREAMscript--the native tongue of VREAM's own VRCreator tool. VRCreator adds dimensions of realism not possible with VRML, including penetrability, elasticity and throw-ability.

For an advance preview, check out the example VRML worlds already on file at the San Diego Supercomputer Center's VRML Repository .

Other example VRML-based sites .

After June 1, 1995, a new site including much information on VR and including a virtual theme park will open.

Also, the First Annual VRML Symposium will be held December 13 to 15, 1995, at the San Diego Supercomputer Center, San Diego, California (contact webmaster@sdsc.edu ).

ASC puts new twist on superconductors

By Chappell Brown

WESTBOROUGH, Mass. -- American Superconductor Corp. is claiming a breakthrough in building low-loss ac power lines with high-temperature superconductors. The new conducting lines are structured as bundles of filaments twisted around one another, a configuration that minimizes energy loss. While dc superconductors can achieve near-perfect lossless transmission, alternating currents generate electromagnetic side effects that disturb current flow.

Prototype conductors using the new technique showed critical current densities above 10,000 A/cm2 at 77 K.

"This development o pens the door to a wide range of alternating-current applications," said Alex Malozemoff, American Superconductor's chief technical officer. "We know how to build straight multifilament conductors. The question was whether we could do the same thing in a twisted configuration." The new process worked out better than expected, he added.

Stress-induced defects are the principle liability in any attempt to twist superconducting filaments. A "powder-in-tube" process is used at American Superconductor for forming superconducting wires.

All systems go for sensor standard

By Terry Costlow

BOSTON -- The IEEE and NIST committees that are attempting to create an interface standard for sensors showed a prototype of their draft specification at the Sensors Expo here earlier this month, getting solid enough encouragement to proceed with the completion o f the document.

It established three working groups that will address four areas. One is a standard output range, probably 0.5 to 4.5 V, another is that analog sensors should all have a single power supply, such as +5 V. The committees will also focus on the incorporation of a Transducer Electronic Data Sheet (Teds) and create a standard analog sensor model that will be represented in a Teds.

"We are planning to come up with a draft by the end of the year. That's a very aggressive schedule," said Kang Lee, leader of the sensor integration group at the National Institute of Standards and Technology (Gaithersburg, Md.).

The group members are working only on connection to existing networks, so they are not creating new digital interfaces. They are also currently focusing their efforts on transducers, avoiding new types of sensors.

Interested parties can voice their opinions by downloading the IEEE/NIST poll from the EE Times-interactive WWW home page and faxi ng it in.

Asians add IC auto-assembly

By Ashok Bindra

CHAM, Switzerland -- Rapid growth in IC production in Asia is prompting semiconductor companies there to take a hard look at automated IC-assembly lines. One vendor being eyed with interest is ESEC SA, which provides many of the assembly turnkey systems being used in Southeast Asia.

Swiss-owned ESEC claims to have completed the first installations of its integrated Autoline at the assembly facilities of seven major semiconductor houses in Singapore, Korea, Taiwan and Indonesia. ESEC president Karl Nicklaus defined Autoline as a flexible, fully automatic, front-of-line assembly solution.

The turnkey system integrates a die bonder, epoxy-curing system, multiple wire bonders, optical inspection and automatic molding. It can be managed by a single operator, with no manual intervention requ ired throughout the IC-assembly process, said Mark DiOrio, ESEC's vice president of marketing. The system is modular, permitting better utilization of equipment and substantial improvement in yield, DiOrio added.

VGA-to-NTSC encoder chip developed

SAN JOSE, Calif.--Chrontel, a rapidly-growing Silicon Valley mixed-signal house, has put everything necessary to convert VGA to NTSC into a single chip, along with a number of features valuable to the resulting image quality. The CH7001 VGA to NTSC/PAL Encoder includes triple video ADCs, filters, scan rate and color space converters, a modulator, color-burst and sync generation and triple video DACs, all on one chip.

The display of choice for home entertainment is--and is likely to stay--the TV set. Consequently, most home computers will someday have NTSC or PAL composite video outputs as a matter of course. But NTSC video from a computer is sti ll a relatively new idea: most home users who connect their game-playing PC to a TV monitor use some sort of converter box.

And these boxes can be quite complex. The analog RGB and clock signals from the graphics card have to be captured and converted to digital form. Then the signals have to be processed to deal with the differences in resolution, timing, aspect ratio and scanning (progressive vs. interlaced) between a VGA monitor and a TV set.

In addition, the signals have to be converted from RGB color space to YUV color space. The signals have to be remodulated, color bursts and sync information added and the whole thing converted back to analog.

If being able to do all this in a single chip isn't enough to raise some eyebrows in the home computer community, the price may do the trick--the 44-pin PLCC costs $25 each in 20,000 volumes.

Chip set aids dual-processor servers

By Ron Wilson

SAN JOSE, Calif. -- After the recent flurry of updated Peripheral Component Interconnect (PCI) chip sets for the Pentium processor, the desktop core-logic business has settled down--but not so the server business. The people working to turn a handful of Pentium chips into a multiprocessing server have a number of unique problems, and so far they haven't gotten much help from the chip-set vendors.

Most server companies have looked over their alternatives and chosen to design their own core logic. Still, many of the companies being attracted by the expanding market and splendidly high margins for servers lack the capital or engineering horsepower to design such a system from the ground up. Hence, there is an emerging market for off-the-shelf server core logic.

Anticipating that trend, Acer Laboratories Inc. has been designing multiprocessor core logic for a number of years, trying ideas, building silicon and waiting for the idea to catch on. This may be their day.

To seize it, Acer has pulled designs and actual chips from two prior core logic sets to create a dual-processor logic set for Pentium-class servers. The set works with Pentium, Advanced Micro Devices K5 and Cyrix M1 chips, and it complies either with Intel Corp.'s Advanced Programmable Interrupt Controller (Apic) architecture or with Compaq's SystemPro architecture--the one, Acer points out, for which all the existing software was written.

Intel has been explaining how easy it is to put two Pentium chips together in a symmetric multiprocessing arrangement--and, indeed, all the hooks are in the CPU. But there is a lot of fine print involved.

One problem is that Intel's approach shares one secondary cache between the two CPUs. That may be great for benchmarks, but it may be less so in a rich, multithread environment, such as those promised any day now for servers.

IC hopes to shine a t the office

By Ron Wilson

PULLMAN, Wash. -- As office-equipment designers move toward the ultimate office machine--the combined scanner, fax, printer and copier--they are creating the ultimate memory bottleneck. The amount of bit-map information that must flow through the printer's local memory becomes so large in such a system that the designer may be pushed toward premium-priced, specialty memory chips--a decision inconsistent with the cost requirements of the market.

One solution is to compress the image data before it goes into memory and to expand it again on its way to the print engine. Lossless data compression can achieve compression ratios of anywhere from 4:1 to perhaps 20:1, substantially reducing the data traffic through memory.

But that requires on-the-fly compression of incoming data and real-time decompression of data headed for the laser. Those two tasks are too heavy to dump on the already busy CPU, even for systems using a 32 -bit embedded RISC chip. And it's costly to outfit the printer with a pair of dedicated compression chips.

Advanced Hardware Architectures, which has been doing lossless compression for some time, has a possible solution. The company recently announced the AHA3410 StarLite chip, which can do simultaneous compression and decompression at 25 Mbytes/second in each direction.

In a printer environment, the StarLite would, for example, take data in from a scanner and from the output of a Postscript parser. It would compress the data on the fly and send it to local memory. At the same time, under control of the local CPU, the chip would pick up bands of data from the local memory, decompress them and write them to the print engine.

Cold Warriors look back on first sky spy

By George Leopold

WASHINGTON -- For 12 years, the world's first spy satellit e photographed an estimated 750 million square nautical miles of the planet during 94 missions. It pinpointed Soviet strategic targets with such accuracy that in one shot you can actually see the line of people entering Lenin's Tomb in Red Square. Above all, the satellite, called Corona, provided irrefutable evidence to debunk the myth of the "missile gap" of the late 1950s. And it did all this in utter secrecy.

The aging Cold Warriors who designed, built and launched Corona in 1960 gathered here last week with the photo analysts and CIA officials who made momentous decisions based on Corona's intelligence. They revealed for the first time the story of government-industry cooperation, stealth and flat-out deception that made the historic photoreconnaissance program fly.

The reunion--part of a CIA-sponsored symposium on the highly classified spy program-- was occasioned by the Clinton administration's decision in February to declassify satellite imagery collected by Corona and two other spy-satellite pr ograms.

Making his first speech since being confirmed as director of a new and improved Central Intelligence Agency, John Deutch reminisced about the days when the CIA, the Air Force and aerospace-industry engineers could move a top-secret spy satellite from drawing board to launching pad in three years.

Sun hitches UltraSparc to Intel PCI bus

By Michele Clarke and Ron Wilson

SAN FRANCISCO -- Breaking with its current system architecture, the Sparc Technology Business of Sun Microsystems Inc. last week unveiled a novel bus scheme for the UltraSparc CPU and vowed to use Intel Corp.'s Peripheral Component Interconnect (PCI) bus in future products.

Taking the wraps off an UltraSparc reference platform here, Sun eschewed its open-standard MBus and showed instead a new 216-signal, packet-switching bus, a pr oprietary core-logic chip set employing 18 BiCMOS crossbar switches and a road map to move Sun workstation peripherals onto PCI.

The initial reference design is a uniprocessor, SBus-based system. But SBus will soon be phased out, and future designs will include dual-bus systems, bringing the PCI bus into Sun machines for the first time.

The new design served notice to Sparc OEMs--and to competitors like Fujitsu's Ross Technology business--that Sun would no longer provide an open MBus platform accessible to other people's CPU modules. Instead, the Net.Core platform, as Sun called the design, uses UltraSparc Port Architecture (UPA).

Where MBus is a conventional broadcast bus, UPA is a distributed-arbitration multimaster packet-switching scheme. It was designed to minimize latencies for systems that include multiple version-9 Sparc CPU modules.

Sun MP link aims to boost workstations

By Alexander Wolfe

MOUNTAIN VIEW, Calif. -- Aiming to squeeze supercomputer-class performance out of workstation clusters, Sun Microsystems Computer Corp. (SMCC) has developed a 4-Gbit/second optical interconnect technology that it claims can outperform rival approaches.

Many academic researchers have been attempting to enable networks of workstations to function as virtual parallel processors (see Sept. 5, 1994, page 1). But the Sun effort--called S3.MP, for Sun Scalable Shared-memory Multi-Processor--appears to take a more ambitious tack.

Andreas Nowatzyk, the SMCC staff engineer who is leading the project, and his colleagues will outline their work next month at the IEEE/ACM International Conference on Computer Architecture in Margherita Ligure, Italy, and at the Hot Interconnects Symposium at Stanford University (Stanford, Calif.) in August.

S3.MP's initial incarnation uses one CMOS ASIC to manage the high-speed link and its companion adaptive router algorithm, and another to maintain the integrity of memory--long a bugaboo in parallel-processing setups. By placing intelligence into these special-purpose chips, the approach is said to markedly reduce the performance drags that have plagued other methods.

"I believe we have developed a compelling technology," said Nowatzyk. "The goal is not multiprocessing ý la Cray Research. We would like to make it as cheap as possible, via a single component on the motherboard. In the future, we see it as being part of the processor itself.

Moto to rejuvenate DSP line to regain merchant dominance

By Martin Gold

AUSTON, Texas -- Looking to regain a dominant position in the merchant digital-signal-processing market, Motorola's DSP division has been hard at work developing two DSP core families, EE Times has learned. The effort could intensify the pitched batt le for design wins in the emerging personal-communications and wireless sectors.

Motorola will move into high-end digital-cellular territory with its 24-bit 56300 DSP core--code-named Onyx--which will debut in the fourth quarter. The core will initially deliver 66 Mips (66 MHz) at 3 V, with an eye toward 100-Mips performance.

That will be followed by a 16-bit 56800 core, code-named Hawk, which is intended for cost-sensitive applications such as pagers and wireless handsets. Hawk will become the heart of new devices that deliver 20-Mips (40 MHz ) performance at 3 V. There will also be 10-Mips devices operating at 2 V.

"We intend to continuously spin-off new cores and new devices in the same way that we spun-off so many derivatives from our original 8-bit microcontroller core," said Jim George, corporate vice president and general manager of Motorola's DSP division.

National, Samsung, Toshiba push NAND flash into future

By Ron Wilson

SAN JOSE, Calif.--Not content with acceptance in the solid-state storage market, three key vendors of NAND-type flash memory--National Semiconductor Corp., Samsung Corp. and Toshiba Corp.--are pushing the technology in unforeseen directions. More EPROM-like architectures, multilevel memory cells and applications in the mixed-signal world may all be in the cards.

NAND flash, because of its inherently small cell size and fast serial access, was originally billed as a solution for disk replacement in portable and ruggedized systems. And that in fact seems to be the market in which it is catching on fastest.

The advent of 16-Mbit flash chips and the appearance of AT bus attachment (ATA) disk-emulating controllers from Cirrus Logic Inc. and IBM Corp. have heightened demand for NAND-type flash in disk applications. "At the same time that flash prices are coming down, the disk vendors' focus on high-density techno logy is driving their minimum prices up," said Samsung Electronics business team director Syed Ali. "That is opening the window for solid-state storage.

"One result is that our 16-Mbit flash chip is now shipping between 75,000 and 100,000 units

a month."

Sharp to establish U.S. research arm

TOKYO -- Sharp Corp. is setting up an applied research center at Camas, Wash., and plans to hire about 100 people for multimedia-related R&D.

The operation, called Sharp Laboratories of America (SLA), will be headed up by Jon Kaufmann Clemens, former senior vice president at the Stanford Research Institute.

Advanced television systems, next-generation image- compression technology including MPEG-4, set-top-box technology for digital CATV systems, and PDA-based communications technology will be the primary research areas.

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