EET-i Top of the News
Week of May 8, 1995
- May 11, 1995
 NEC, Rambus threaten RAMDACs
- Mentor sets systems-on-silicon strategy
- Microsoft gives sneak peek at MITV
- Popularity of BGAs leads Amkor to announce U.S. plant
- Davic group close to adopting set-top standard
- Germany's Escom buys Commodore
What's new(s) at EE Times-interactive
- May 10, 1995
- Emulation startup to take on Quickturn, Zycad
- IBM to second-source Ramtron DRAMs
- TI launches wireless DSP architecture
- It's a consensus: the PC will pervade everything
- HLD taps ASIC vendors
- Philips takes on Intel in 16-bit mi
crocontrollers
- May 9, 1995
- German researchers developing hardware/software codesign system
- NASA builds 3-D learning network
- VLSI preps embedded DSP core, real-time OS
- Micro Substrates creates inexpensive ceramic BGA
- Cisco routers now compatible with IBM's SNA networks
- DEC merging VMS, NT
- Philips claims 22V10 speed crown
- IBM offers 200-MHz sync SRAM
- May 8, 1995
- LCDs go trucking on as SID spotlights tomorrow's improved versions
- Zycad storms into FPGA market
- Communications circuits dominate Custom IC Conference
- IPC on verge of a CAD-to-CAM transfer format
- Computer Big 5 Unveils Nine Requirements for DVD
Other news sources on Techweb:
NEC, Rambus threaten RAMDACs
By
Ron Wilson
MOUNTAIN VIEW, Calif. -- On Monday, NEC Electronics Inc. and Rambus Inc. will launch a demonstration graphics chip that may signal the beginning of the end for stand-alone high-performance RAMDACs. The chip, intended as both a guide to NEC ASIC customers and a technical demonstration, tramples current technology with 1-Gbyte/second raw frame-buffer bandwidth and an integral 170-MHz, 27-bit RAMDAC cell.
Called the Rambus Universal Graphics Back End (Rugbe) chip, the device is a very fast, dumb, linear frame buffer. The chip comes with a PCI interface on the system side and a pair of Rambus channels connecting to two 16-Mbit Rambus RDRAMs. It will be available only
as a development vehicle to NEC customers.
Logic design was done by Rambus, while the RAMDAC was designed by NEC's ASIC design center here.
The design is significant for several reasons, said NEC senior marketing manager Roy Dasilva. Combining a pair of Rambus channels on one ASIC produces higher bandwidth than can be had with even advanced video AM (VRAM) designs. At the same time, the entire graphics subsystem comprises three chips-a significant reduction from the footprint of current high-end systems. For a direct comparison, of course, the NEC chip would have to include Super VGA, BitBLT and drawing hardware, which this particular chip does not. But such hardware would easily fit on a moderately sized die in the 0.5-micron process NEC used for the demonstration.
Mentor sets systems-on-silicon strategy
By
Richard Goering
WILSONVILLE
, Ore. -- In an attempt to forge a new corporate identity, Mentor Graphics this week announced a "systems-on-silicon" initiative that will set the stage for future EDA software products and services. Mentor also unveiled a comprehensive 10-year alliance with LSI Logic Corp. (Milpitas, Calif.) that will help enable the initiative.
In other announcements this week, Mentor acquired Axiom Daterer Skandinavien, a small Swedish firm that provides schematic-symbol generation; rolled out a Parts Development System Manager; reinforced its design-for-test efforts with new personnel and services; and hired Pepe Piedra, former president of NeoCad Inc., to serve as vice president and general manager of new business ventures.
Though the company continues to be active on many fronts, the systems-on-silicon initiative could become the single focal point that Mentor has generally lacked in the past. "I truly believe that during the next few years, systems on silicon and the problems related to it will redefine EDA," sai
d Wally Rhines, Mentor Graphics president and CEO.
While people have been talking for years about integrating systems onto single chips, there's a trend in which designers are building new systems "from the ground up" using ASIC cores, random logic and memory and data-path elements, Rhines noted. That's a step up from shrinking an existing pc-board onto a chip, or wrapping some random logic around a DSP core. And with it comes compelling challenges in such areas as design reuse, tool performance and capacity, and design-flow management.
Alliances with semiconductor vendors are key to meeting those challenges, and that's where Mentor's pact with LSI Logic comes in. The two companies will cooperate in library development, test generation, non-linear delay modeling in support of deep-submicron design, and customer support and training.
"If you want to do systems on silicon today, you have to go to LSI Logic, Motorola, Texas Instruments or VLSI Technology," observed Gary Smith, analyst at Dataquest Inc.
"The EDA vendors can't do it. This [alliance] seems to be a swap; Mentor helps LSI with its deep-submicron problems, and LSI gives Mentor the capability to do systems on silicon. If they pull it off, it will be significant."
Microsoft gives sneak peek at MITV
By
Junko Yoshida
DALLAS -- Adding more confusion and choices to a still-nascent interactive TV market, Microsoft Corp. demonstrated its interactive TV platform, designated "MITV" (Microsoft Interactive Television), at the National Cable Television Association (NCTA) '95 show this week.
The new operating system, still in R&D and with no plans for commercial rollout before 1997, uses interactive-TV software elements Microsoft has developed over the last two years.
Built on the Windows infrastructure, the MITV operating system supports a portion of Win32 code for Windows NT, shar
es a subset of Windows 95 Games API and employs a distributed implementation of Microsoft's Common Object Model (COM) for sending objects over networks, said Mike Beckerman, group program manager at Microsoft+s Advanced Consumer Technology (ACT) Infrastructure & Services.
MITV needs "about 1 Mbyte of memory to run the whole operating system, with a small kernel of about 128k," said Alan Yates, business development manager, Home Electronics, Advanced Consumer Technology at Microsoft.
Microsoft last week also showed off its strategic alliances with four set-top vendors: Hewlett-Packard, Sony, NEC and General Instrument. Through MITV, Microsoft hopes to corner a dominant share of the second-phase interactive TV market, focused on the Full Service Network (FSN) deployment.
Popularity of BGAs leads Amkor to announce U.S. plant
By
David Lammers
SINGAPORE -- Amkor Electronics Inc. has announced plans to complete the first non-captive ball-grid-array (BGA) packaging facility in the United States by the end of next year. That move, and the acceptance of BGA-packaged chip sets by Compaq Computer Corp., Dell Computer and other personal-computer companies, is a sign that BGAs have come of age, participants in the recent Semicon Test, Assembly, and Packaging show here concurred.
High-end ASICs, PC chip sets, synchronous SRAMs and other high-pin-count devices are moving away from quad flat packs, partly because the assembly yield for BGAs is higher than for the ultra-fine-lead flat packages.
Corporate vice president Mike O'Brien said Amkor (Chandler, Ariz.) and parent Anam Electronics (Seoul South Korea), the world+s largest contract assembler, together "have big expansion plans" under way in Chandler, Seoul and Manila, Philippines. Anam's Seoul facility will increase its BGA-packaging capacity from about 320,000 units per week now to 700,000
per week by year+s end. The Chandler facility is expected to be ready by late 1996.
Davic group close to adopting set-top standard
By
George Leopold
ROME -- An international standards group cleared several major hurdles last week in its efforts to complete interoperability standards for digital set-top boxes by December. However, U.S. industry members say the group must still overcome a noise problem that could interfere with cable transmission, and then convince both European cable and satellite companies to embrace their proposals.
A consensus was reached among Digital Audio-Video Council (Davic) members at last week+s meeting, which was held here, to adopt General Instruments Inc.'s (GI) quadrature amplitude modulation (QAM) as the group's modulation scheme-initially based on a 64-QAM version but eventually moving to 256-QAM. Davic's u
nanimous vote for QAM "shows that we're going to have a very well-supported, frozen spec," said Robert Luff, chief technical officer for Scientific-Atlanta Inc.'s Broadband Communications Group and a member of Davic's management committee.
Germany's Escom buys Commodore
BOCHUM, Germany -- Escom AG, a German computer maker, has acquired the assets and intellectual property of Commodore Electronics Ltd. and some of its units, including worldwide rights to the Commodore and Amiga trademarks and patents.
As a result, Escom has acquired Amiga's patented technologies, which Escom said will provide it with key technology to become a multimedia leader in the consumer market. Escom plans to develop TV set-top boxes based on the Amiga technology.
Escom intends to make the entire Amiga product range, including the A1200 and the A4000, and to integrate Amiga technology into the MS-DOS format.
P
art of Escom's plan is to sell the technology into Eastern Europe and the Far East.
In addition Escom has entered into a joint venture with Tianjin Family-issued Multimedia Co. Ltd (TFM) in China under which TFM will begin production and distribution in China of computers based on the Amiga technology.
Emulation startup to take on Quickturn, Zycad
By
Brian Fuller
CAMBRIDGE, Mass. -- A startup emerging from the halls of MIT is setting out this year to tackle the tricky emulation market, now dominated by companies such as Quickturn Systems and Zycad.
Virtual Machine Works will begin shipping beta versions of its product, which is based on a technology the company calls VirtualWires, in July. Commercial shipments aren't expected until January 1996.
"Although the technology has a variety of applications, it was clear early on that it c
ould be greatly leveraged in a prototyping or emulation situation," said William Fletcher, a former manager with Cadence Design Systems Inc. (San Jose, Calif.) who is Virtual's vice president of marketing and sales.
Taking the wraps off the company in interviews this week, Virtual Machine managers kept product details vague.
Anant Agarwal, associate professor of computer science at MIT who founded the company, said the idea behind the technology is to a bring less-expensive, easier-to-use emulation solution to bear on both the high-end and moderate segments of the ASIC design community. To date, emulation solutions have been a must for the most advanced ASIC and full-custom designs, and the several-million-dollar price tags have kept simulation a necessary verification alternative for less-sophisticated designs.
IBM to second-source Ramtron DRAMs
By
Loring Wirbel
COLORADO SPRINGS, Colo. -- Ramtron International Corp. has signed IBM Microelectronics' Essex Junction, Vt., facility as a much-needed second source for Ramtron's enhanced-DRAM products. The IBM fab will provide Ramtron with EDRAM dice for densities of 4 Mbits and above, in addition to producing its own memory devices under the IBM Microelectronics label.
EDRAMs combine a traditional DRAM array with a static-RAM cache to achieve access times down to 15 ns. Ramtron has taken large orders for EDRAMs from such OEMs as Ocean Office Automation Ltd., but it has built up backlog because of capacity constraints at its primary foundry, Nippon Steel.
EDRAM is finding favor in many designs, with some applications treating the device as a direct SRAM replacement rather than a graphics memory. When introduced, the EDRAM was pitched as a competitor to burst-extended-data-out memories for graphics applications. But Todd Oseth, vice president for Ramtron's Specialty Memory Division, said
the device is holding its own against special system-bus memories, such as Rambus, as well as against standard SRAMs.
TI launches wireless DSP architecture
By
Loring Wirbel
HOUSTON -- Texas Instruments Inc. is shoring up its growing presence in digital-cellular handsets and base stations by launching a dedicated 16-bit fixed-point architecture for cellular and Personal Communication Service (PCS) applications. The TMS320C54x family was hinted at last fall, when TI launched its Low-power Enhanced Architecture DSP (Lead) program in Japan.
With this release, TI is offering the first two standard-product members of a family that is expected to grow significantly in the next two years.
The generic C54x core features new hard-wired functions, such as a Viterbi-coding accelerator. It will be offered as a general DSP customizable core, and it
will be used in standard products. Spin-offs of the earlier 16-bit TMS320C5x family have already been used in IS-54 and other digital-cellular programs.
But Gilles Delfassy, manager of the wireless communications business unit, said that the C54x family is more than a simple enhancement to the C5x family. Dual accumulators and special buffered serial ports have been added.
"This core will be the basis for several standard products you'll be seeing in coming months, though we expect a significant number of customers will want custom versions of the architecture," said Thomas Brooks, TMS320 wireless product marketing manager.
It's a consensus: the PC will pervade everything
By
Martin Gold
and
Brian Fuller
SCOTTSDALE, Ariz. -- Serving as the next battleground for the electronics industry, the home wil
l be invaded by the personal computer, which will lead the charge through consumers' front doors. The PC will forge ahead not only in its current incarnation but as an evolving platform that will control everything from entertainment to security.
But while the personal-computer's ubiquity and relatively open architecture make it a natural selection for proliferation into the home, the electronics industry has to overcome daunting obstacles to position PCs in a market where low cost and ease-of-use are of paramount concern.
That was the consensus here earlier this month at the 11th In-Stat Microelectronics Forum, where industry executives agreed that the PC will be the emerging consumer platform.
E-mail and faxing, conferencing, on-line access and client-server applications will become as commonplace in the home as word processing and spreadsheets were in the late 1980s, said Carl Stork, director, Windows Hardware Programs at Microsoft Corp. However, for this next generation of machines, chip vendors
will be responsible for delivering higher-speed microprocessors, higher-density DRAMs, new mass-storage media and a new generation of mixed-signal circuits that enable easy Internet access--all at low cost. "The x86 processor can deliver the price and performance for the desktop PC in the time frame I can see," Stork asserted.
"The latest technology will be needed to create appeal for consumers. In addition to price, they will be looking for more performance, audio/video capabilities and an ability to have fun," Stork added. "If the PC industry turns out machines that appeal to the home market and the very large number of new business users, the opportunities for the semiconductor industry will be enormous."
HLD taps ASIC vendors
By
Richard Goering
SANTA CLARA, Calif. -- In an attempt to extend floor planning to ASIC design, High Level D
esign (HLD) Systems has launched a Deep-Submicron ASIC Vendor Program aimed at developing libraries and methodologies in support of HLD's Design Planner tools. Atmel Corp., IBM, Mitsubishi Electronics, Oki Semiconductor and Symbios Logic have announced their participation in the program.
According to Bob Wiederhold, vice president and COO of HLD Systems, the program signals a shift in the use of floor-planning tools. While custom-IC designers have so far been the main users of such tools, ASIC designers are starting to consider them for deep-submicron designs. That means ASIC libraries must be provided for floor-planning tools.
"It's not like putting together a simulation library, where everyone knows how to put one together," said Wiederhold. "We're entering some uncharted waters here." As such, he noted, a crucial part of the program is working with ASIC vendors and their key customers to refine deep-submicron design methodologies.
Philips takes on Intel in 16-bit microcontrollers
By
Bernard C. Cole
SUNNYVALE, Calif. -- Philips Semiconductors has moved its microcontroller competition with Intel Corp. into the 16-bit arena with the introduction of the 8051XA, a 16-bit extension to the venerable 8-bit 8051.
Just a month ago, Intel started producing the first in its 80251 family of 8051 extensions, offering a clear migration path to 16-bit performance by means of a hybrid 8-/16-bit architecture. The hybrid allows 8051 developers to migrate their original, 8-bit source code without alteration, to achieve a fourfold to tenfold improvement in throughput.
The Philips 8051XA targets not only 8-bit microcontroller users but also such 16-bit design slots as those filled by Intel's 80196 family, which dominates the 16-bit segment. Indeed, most of the benchmarks Philips is quoting to promote the XA do not measure the architecture against earlier
8051 designs or even the new Intel 80251, but against the 80196.
Philips microcontroller marketing manager Mike Thompson said the first member of the XA family, the 8051XA-G3, has been measured by a number of industry-standard benchmarks and has been calculated by company engineers to be two to three times faster than the 80196 at the same clock rate. At 30 MHz, he said, the XA-G3 has a typical instruction-execution time of 100 ns, compared with 200 to 300 ns on the 80196.
German researchers developing hardware/software codesign system
By
Peter Clarke
SANKT AUGUSTIN, Germany -- A research project in the emerging field of hardware/software codesign at the German National Research Center for Computer Science will quickly move into the commercial arena with a plan to license the project's design tools to EDA vendors by the end of this year. A
software suite called Castle (Codesign and Architecture-driven Synthesis Tool Environment) provides designers with a high-level view of an architecture that features flexible hardware/software partitioning of system functions.
"We expect to have a reasonably stable prototype available by the end of the year," said Theodor Vierhaus, who is in charge of the Castle program. Castle is the research center's contribution to a three-year program that ends this year, called Sydis, which involves a number of German research institutes and two industrial partners, Robert Bosch GmbH (Stuttgart) and semiconductor company Thesys GmbH (Erfurt). Those two companies have access to early versions of the software that is being applied to real-world problems to test the tools and benchmark the efficiency of the methods and algorithms.
Like many design systems, Castle starts from a high-level behavioral representation and generates a structural VHDL description at the register transfer level. However, the system also gene
rates C code software that runs on the hardware described in the VHDL file, a unique aspect of hardware/software codesign.
NASA builds 3-D learning network
By
Loring Wirbel
COLORADO SPRINGS, Colo. --NASA's Jet Propulsion Laboratory (JPL) is building prototypes of a 3-D "sugar cube" combining an adaptive-learning network with a ferroelectric memory structure. The purpose of the project is to develop a self-learning imaging platform capable of fast Fourier transforms and image filtering on missions to the outer solar system. A compact system that performs the early steps of image processing on the space craft will greatly reduce the the amount of image data sent back to Earth.
Sarita Thakoor, who manages special microelectronics programs within NASA's Pasadena branch of JPL, described the sugar cube in a special session at the recent Seventh I
nternational Symposium on Integrated Ferroelectrics held here. She said that early prototypes have used traditional SRAMs in conjunction with neural networks, but that the team would like to switch to ferroelectric memories for better power consumption and data retention features.
JPL researchers are reviewing several possible neural-network architectures for the image processor. Many researchers described the direct integration of ferroelectric field-effect transistors into Hebbian adaptive-learning architectures, but NASA is not yet looking at this level of integration. Instead, standalone neural-network hardware arrays will feed independent memory arrays. The first prototypes of these 3-D systems use SRAMs. For nearer-term missions such as the Mars Pathfinder mission, such "sugar cube" arrays might have to use SRAMs, Thakoor said.
However, "if larger-density FRAMs are available relatively soon, we would be able to incorporate them into 3-D arrays for missions scheduled within just a few years," she s
aid.
VLSI preps embedded DSP core, real-time OS
By
Junko Yoshida
SAN JOSE, Calif. -- VLSI Technology Inc. is ready to announce availability of an embedded digital-signal-processing approach, based on the DSP Group's Pine DSP core, that will be supported by a real-time mulitasking operating system written by Belgium-based Eonic Systems. VLSI hopes to leverage its Pine license and Eonic's Virtuoso OS--which is billed as smaller and better-tailored to 16-bit fixed-point applications than Spectron Microsystems' Spox--to capitalize on the market's shifting momentum from standalone DSP products to DSP-core-based ASICs.
The VVF3000 embedded DSP core is claimed to achieve 40-Mips performance at 5 V, 33 Mips at 3.3 V and 30 Mips at 3 V. VLSI will offer both software- and hardware-development tools, and Mentor Graphics Corp.'s DSP Station will support
the VVF3000 high-level functional model for architecture-trade-off analyses.
Noting that the market emphasis in DSPs is shifting to core-based application-specific approaches, Chris Vance, U.S. DSP marketing manager at the VLSI Products Division, said the company's "true ASIC approach, combined with a broad range of functional-system-block cells, allows us to go after the sweet spot in the market." He said VLSI will benefit from its mixed-signal experience in integrating analog converters with digital ASICs for GSM and DECT chip sets.
Micro Substrates creates inexpensive ceramic BGA
By
Ashok Bindra
TEMPE, Ariz. -- Micro Substrates Corp. (MSC) has extended its patented Via/Plane process to develop a low-cost ceramic ball-grid-array package offering high I/Os at a cost of less than 2 cents per ball. By comparison, MSC said, other ceramic BGAs
can cost 5 cents per I/O.
Via/Pak BGA provides the density and power capabilities of ceramic while being cost-competitive with plastic BGAs, said MSC president Ram Panicker. It also provides substantial cost savings over multilayer co-fired packages, Panicker said. The company is sampling a 361-ball Via/Pak BGA, with production slated for the fourth quarter. While other custom versions are also in the works, MSC said that two major semiconductor companies, one in Japan and one in the United States, are investigating the use of a 361-ball BGA in high-performance ASICs, microprocessors and microcontrollers.
The package is being qualified for electrical, mechanical and reliability performance. The ball pitch is 0.05-inch (50 mils), with the diameter of each ball being 0.035-inch (35 mils). According to MSC, the Via/Pak BGA offers a lead planarity of ý1 mil. It comes in an area-array format with a grid of 19 x 19 balls. The 90-percent lead balls are attached to the grid using eutectic solder, said the manu
facturer. TheVia/Pak, a 0.984-inch (25 mm) square only 0.04 inch (1 mm) high, is a chip-scale package suitable for applications that require light weight and low profile, Panicker said.
Cisco routers now compatible with IBM's SNA networks
By
Loring Wirbel
RESEARCH TRIANGLE PARK, N.C. -- Cisco Systems Inc. has completed its five-year, five-phase plan to offer router customers full Systems Network Architecture (SNA) options for IBM data traffic, including peer-to-peer traffic as defined in IBM's Advanced Peer-to-Peer Networking (APPN) standards. Most features of native APPN routing will be delivered to customers in the third quarter, and a free upgrade to IBM's High Performance Routing (HPR) protocol will be shipped to customers by January.
The plan's completion comes simultaneously with Cisco's consolidation of all IBM-related router developme
nt in a new IBM business unit here. On May 5, Cisco and IBM signed a pact that passed over to Cisco all joint IBM/Kalpana Inc. work on switched Ethernet and token-ring hardware--the first peace pact since Cisco unexpectedly acquired Kalpana last October. A Cisco spokesman said that combined work on APPN, SNA hardware and LAN switching within the IBM business unit has taken Cisco's head count in North Carolina to more than 200.
DEC merging VMS, NT
By
Michele Clarke
MAYNARD, Mass. -- Officially announcing plans last week to merge its venerable Open VMS operating system and Microsoft's Windows NT, Digital Equipment has set the stage for a graceful transition of its aging code base.
Digital will phase the Win32s application programming interfaces (API) into OpenVMS this year. Additionally, it will build support into OpenVMS for the Microsoft Fou
ndation Class libraries and Microsoft's Object Linking and Embedding (OLE) 2.0 technology.
The server-oriented Windows NT APIs will be added to OpenVMS next year. The new OS revisions will ultimately enable developers to write code for Windows NT that will run on OpenVMS systems without modification.
At that point, the company will tell independent software vendors to stop developing for OpenVMS, said Ken Swanton, director of OpenVMS product marketing. "Initially, there will be some things that programmers will have to be aware of [to enable their Windows NT code to run on OpenVMS systems], but over time, they'll become oblivious [of them]."
The impetus for the strategy, added Swanton, is that OpenVMS has needed "a wider array of killer server applications" for a while. "Our customers want the bulletproof features of OpenVMS, but they also want the latest applications. We believe this plan gives them both."
Philips claims 22V10 speed crown
By
Ron Wilson
ALBUQUERQUE, N. M. -- The battle continues for the world's fastest 22V10 PAL as Philips Semiconductors fires its 5-ns ABT22V10A5 that lacks the raw speed of Cypress Semiconductor's 4-ns part, but intends to be faster in actual applications.
While propagation delay is a vital factor in state-machine design, the sum of set-up time plus hold time plus propagation delay can turn out to be the limiting number for maximum clock frequency. In the Philips part, the set-up time is 2 ns, a full 500 ps faster than that for the Cypress 22V10. Hold time on the Philips part is, as on most modern PLDs, zero. That would appear to make the total path through the Philips part about 500 ps longer than through the Cypress part for internal feedback paths. If external feedback is used in a synchronous design, the Philips device has a 4-ns clock-to-out time that also has to be figured in, and might give it th
e edge. In any case, both parts are capable of performance at extremely high clock rates.
IBM offers 200-MHz sync SRAM
By
Ron Wilson
FISHKILL, N.Y. -- With all of the attention paid in recent months to synchronous burst SRAMs for Pentium PCs, one might forget that workstations also need secondary caches. And workstations are not content to run those caches at 66 MHz. Consequently, there is continued, if low-key, competition in the market for really fast synchronous SRAMs.
The most recent entry comes from IBM Microelectronics, which has a solid family of 0.5-micron CMOS processes. They are so good that IBM has been able to field a 1-Mbit CMOS SRAM that can challenge existing BiCMOS SRAMs in performance. Whether that is an advantage, given the increasing sophistication of submicron BiCMOS processes these days, remains to be seen.
The new par
ts, designated 043611QLA and 041811QLA, are 32k x 36 and 64k x 18 chips, respectively. They both offer self-timed late write, flow-through and pipelined operation, and byte-write and global-write enable. They use a common I/O scheme and come in standard 7 x 17 ball-grid-array packages.
But the big idea here is speed. In pipelined mode, with the right timing, the SRAMs are capable of 200-MHz operation. That is by virtue of a 2.5-ns access time and a 5-ns cycle time. In flow-through mode -- that is, without the output register -- you get a 7-ns access time and the same 5-ns cycle time.
LCDs go trucking on as SID spotlights tomorrow's improved versions
By
David Lieberman
ORLANDO, Fla. -- The LCD technologies lined up for the Society for Information Display (SID) symposium, which kicks off here on May 21, will illuminate the rapid and relentless
redefinition of liquid-crystal technology to suit a broader range of applications.
Viewing-angle-enhancing, double-domain twisted-nematic active-matrix (TN AM) LCDs, first reported on at last year's SID, are already headed for market, and quad-domain variants are on the drawing board. Prototype polymer-dispersed LCDs (PDLCDs), which require no polarizers and, thus, avoid the major light losses that occur in TN LCDs, promise to double the luminous efficiency of projectors.
Reflective LCDs will be discussed that proponents say willopen the door to portable applications. And SID will see the fall of a cherished assumption about AM The upshot of much of the AM R&D activity, claimed Malcolm Thompson, chief technologist at Xerox Parc (Palo Alto, Calif.). is that "if you think AM LCDs don't look as good as CRTs, then you haven't seen AM LCDs lately."
Zycad storms into FPGA market
By
Richard Goering
and
Ron Wilson
FREMONT, Calif. -- Struggling simulation-accelerator vendor Zycad Corp. last week became the latest company to launch a novel field-programmable gate array (FPGA) architecture. Aiming directly at the mask-programmed gate-array market, Zycad's GateField division has fashioned a flash-memory programming element and a tiled, synthesis-friendly architecture to achieve what the company calls industry-leading density and excellent fit with existing gate-array tool chains.
But issues surrounding Zycad's limited resources and questions about the actual performance of the new parts made it less than clear that GateField can break into the established order of the high-density PLD market.
GateField is the first attempt by an EDA vendor to become a silicon provider. GateField director of marketing Lyle Smith said the new FPGA grew out of Zycad's attempts to develop a logic-emulation s
ystem.
Added Phil Smith, Zycad president and CEO, "A large percentage of our customers are gate-array designers. We live and deal with complex gate arrays. We understand the design problems and we understand verification and prototyping."
Communications circuits dominate Custom IC Conference
By
Loring Wirbel
SANTA CLARA, Calif. -- High-performance communications circuits dominated the Custom Integrated Circuits Conference to a degree seldom seen in past years. High-speed digital controllers and analog interfaces for Sonet/Asynchronous Transfer Mode net works were commonplace, as were RF/IF blocks for emerging 1.8-2 GHz wireless applications.
A CICC session was dedicated to multichip MPEG-2-encoder implementations. And the Thomson Consumer Electronics-LSI Logic Corp. team responsible for the ASIC in the GM/Hughes DirecTV receiver boxe
s provided the first look at the downlink to the digital satellite video system.
Rockwell Telecommunications, in an Advanced Research Projects Agency-funded project conducted with Bell Communications Research Corp. Inc. (Bellcore) and AT&T Bell Labs, showed a GaAs demultiplexer for Sonet OC-192 rates, exceeding 10 Gbits/second.
IPC on verge of a CAD-to-CAM transfer format
By
Terry Costlow
SAN JOSE, Calif. -- Printed-circuit designers could be about to beat the bugaboo of data transfer--converting CAD-software output into formats useable by manufacturing and test systems.
Next week, the Institute for Interconnecting and Packaging Electronic Circuits (IPC; Lincolnwood, Ill.) will meet here with hopes to launch a movement to resolve the data-conversion issue.
"This has the opportunity to be a pivotal meeting," said Thom Dammric
h, executive director at the IPC. "We think we're going to get all levels of the food chain: component suppliers, OEMs, board assemblers, CAD suppliers, CAM suppliers. What will really make it happen is the support of OEMs and the potential for Arpa support."
Computer Big 5 Unveils Nine Requirements for DVD
By
Junko Yoshida
SAN JOSE, Calif. -- The Big Five of the computer business have nailed their requirements for a digital-video-disk (DVD) standard to the doors of the two competing systems even as they urged that the two be merged into a single system.
Nine requirements were listed by IBM, Apple, Compaq, Hewlett-Packard and Microsoft under the aegis of the Technical Working Group, which was formed to press their case. They are: a single interchange standard for both TV- and PC-based applications; read compatibility with exisiting compac
t disks; compatibility with future read-write and write-once disks; a single file system; low cost, comparable to current CD-ROM drives and disks, assuming equivalent volumes; no mandatory caddy or cartridge; reliable data storage and retrieval for read-only, read/write and write-once media; high on-line capacity; high perforamce for both sequential and non-sequential files.
The two incompatible DVD formats are the MultiMedia Compact Disc (MMCD) developed by Sony and Philips, and the Super Density (SD) DVD proposed by a group of electronics and entertainment companies led by Toshiba and Time Warner.
|
RSS
RSS| 
Digital| 
Mobile
