EET-i Top of the News

Week of Feb. 20, 1995

Thursday, Feb. 23, 1995

ISSCC provides glimpse of future of DRAMs
Market for MPEG chips getting complex
Spectron ports SPOX to TI's C80
Pioneer comes to market with MPEG-2 decoder
Micron, National join flash ranks
What's new(s) at EE Times-interactive

Wednesday, Feb. 22, 1995

Microsoft gets behind T.120
Arpa to shift focus in its packaging work
Sharp ramps up TFT line
TSMC mulls fab in West
Five push X-terminal specs

Tuesday, Feb. 21, 1995

Flat-panel process eyed for advanced device designs
Spea prepares low-cost 3-D chip
QuickLogic FPGAs hit 8,000-gate level
SVR recasts IC layout
Megatest VLSI tester aims at the next generation

Monday, Feb. 20, 1995

Taiwan PC makers head toward PowerMac camp
HDCD and DVD may come to a resolution soon
ISSCC banks on a boom in wireless applications
EDA vendors on your team? Cadence, Mentor seek new service model
Dilbert becomes part of the establishment
Actel moves to buy TI's FPGA business

ISSCC provides glimpse of future of DRAMs

By Ron Wilson

SAN FRANCISCO -- The International Solid-State Circuits Conference (ISSCC) looked beyond the excitement over new CPUs and 1-Gbit DRAMs to open a window on the future of silicon design. Researchers at the leading memory companies are pioneering techniques to cope with tiny geometries and 1-V operating voltages. While the resultant chips described at ISSCC probably will never enter production, the experimental techniques and circuits are sure to figure prominently in end-of-decade designs.

One clear view of the future emerges from comparing two 1-Gbit DRAM papers: one from the laboratories of Hitachi Ltd. (Tokyo) and the other from researchers at NEC Corp. (Kanagawa, Japan).

The Hitachi researchers chose to take the most conventional--and most technically challenging--route to a 1-Gbit device: They shrank the DRAM cell to the limits of their laboratory-grade lithography. The result is a DRAM based on an impossibly small, but structurally conventional, cell.

The cell itself uses a stacked capacitor for charge storage. The capacitor cylinders are only 0.6 micron in outside diameter, and their walls are less than 0.2 micron thick. They sit above cell transistors with 0.16-micron channel lengths. The total cell size is only 0.38 by 0.76 micron.

To achieve the desired speed, Hitachi abandoned even the most recent proposals for high-speed, low-voltage interfaces and developed a proprietary ring-canceling output circuit.

NEC used a 0.25-micron process and a relatively vanilla cell structure, resulting in a 0.54-square-micron cell--almost twice the area of the Hitachi cell . That results in a full chip area of 936 mm-square, compared with about 750 mm-square for the Hitachi device.

One reason the NEC chip isn't twice as large is a diagonal-bit-line technique that allows for much closer packing of the memory cells. The next major NEC innovation was to develop an architecture that uses only one sense amp for every eight bit-lines. NEC designed the chip for serial, rather than random, access: The chip accesses a memory block and then reads or writes it in serial order.

Researchers at Mitsubishi Electric Corp. (Itami, Japan) tackled the problems of designing a DRAM with low-threshold transistors. The team came up with a number of circuit innovations, including a hierarchy of global and local power lines, with switches to turn off power buses to reduce leakage current. Manipulation of bias voltages and rethinking of the word-line reduced the bad effects of sub-threshold leakage on the memory cells themselves.

The resulting DRAM circuitry, fabric ated in a conservative two-metal, 0.4-micron process, achieved a 49-ns access time at 1.2 V.

But perhaps the most remarkable demonstration of a low-voltage technique came from a design team at NEC. The team produced a 16-bit digital-signal-processor core that achieved 100-MHz operation at 0.9 V.

The CMOS chip is aimed at mobile-telephony applications, for which DSP power is increasingly important but tiny form factors demand absolute minimum power consumption.

Market for MPEG chips getting complex

By Junko Yoshida

SAN FRANCISCO -- A variety of MPEG-1 encoders is emerging rapidly on the market.

Sigma Designs Inc. (Fremont, Calif.) stole the show at the recent Intermedia conference here by launching what the company calls "the industry's first MPEG authoring solution for less than $4,000," cutting the price of conventional MPEG encoding products by a factor of two to t hree.

FutureTel Inc. (Sunnyvale, Calif.), targeting a much higher quality demanded by video professionals, has demonstrated its real-time encoder family, called The Prime View, starting at $13,900.

By using Motion JPEG encoding software made available by Xing Technology Corp. (Arroyo Grande, Calif.), Fast Multimedia is making available a video-capture board bundled with animation and Adobe Premiere editing tools at $995.

Rick Sizemore, president of market-research firm Total Research MultiMedia (Scottsdale, Ariz.), said, "A real price war is happening now in the encoder market. Whether the picture quality is good or bad, a new level of pricing is going to dictate the market."

Spectron ports SPOX to TI's C80

By Ashok Bindra

HOUSTON -- Texas Instruments Inc. last week announced that Spectron Microsystems' Spox real-time, multitasking operating system has been ported to the TMS320C80, TI's flagship Multimedia Video Processor (MVP). Spox will also be ported to future members of the C8X family.

The move, part of a broader plan to expand the MVP's applications base, follows TI's recent announcement of plans to lower the price of the C80, a 32-bit digital-signal-processing engine that runs at 2 billion operations/second.

Spectron (Santa Barbara, Calif.), meanwhile, said last week that further details of its pending acquisition by Dialogic Corp. (Parsipanny, N.J.) will be announced soon.

The availability of a commercial operating system such as Spox, supported by a comprehensive suite of signal-processing-development tools, will broaden the appeal of the C8X architecture to mainstream designers, said C80 marketing manager Julie Gallagher.

Pioneer comes to market with MPEG-2 decoder

By Peter Clarke

BRISTOL, England -- Japanese giant Pio neer Electronic Corp. steps into the worldwide merchant IC market with an MPEG-2 main-level, main-profile, video-only single-chip decoder designed to work with 16-Mbit synchronous DRAMs. Called the CD1110, the IC decoder was designed by Pioneer's design team, Pioneer Digital Design Center Limited (PDDC), here.

Pioneer has appointed the Memec Group to market and sell the chip in Europe, and Teletronix (Encinitas, Calif.) to sell the CD1110 in North America.

The 710,000-transistor CD1110 is designed for implementation in 0.8-micron CMOS and is being made at an un-named foundry in Japan. Colin Smith, technical director at PDDC, said, "We received samples from the foundry at the end of 1994, and we're working on verifying the device." If the silicon proves itself to be fully working, Pioneer's distributors should be able to provide samples to potential customers in the second quarter.

Micron, Na tional join flash ranks

By Ron Wilson

BOISE, Idaho -- The ranks of flash-memory alternate sources grew last week, as Micron Technologies Inc. disclosed an agreement with Intel Corp. Separately, National Semiconductor Corp. announced first shipment of its Toshiba-derived 16-Mbit NAND flash chip.

Since the flash market continues to look soft, neither announcement is likely to make an immediate impact. But both will play important roles in the strategies of Micron and National.

The Micron-Intel pact includes an exchange of licenses to flash-related patents. "This is a complete patent cross-license," reported Darrell Rinerson, chairman and president of Micron's non-volatile memory operation, called Micron Quantum Devices Inc. "It covers both process and design patents and does involve royalty payments."

The licensing agreement was a necessary prelude to Micron's announcement, in the coming weeks, of 4-Mbit boot-block flash-memory chips. They will be functionally compatible w ith Intel's highly successful boot-block parts. Later, Micron will announce 8- and 16-Mbit devices compatible with Intel's higher-density Smart Voltage flash chips.

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Microsoft gets behind T.120

By Michele Clarke

LEXINGTON, Ky. -- Microsoft Corp. has jumped on the bandwagon that's gathering speed for the still-unfinished T.120 standard for multipoint data conferencing. The software behemoth said it will license a T.120 tool kit from DataBeam Corp. to help build interoperability into its systems software for applications that offer shared "whiteboards."

The set of standards that come under the T.120 rubric address multipoint communications, general conference control, shared whiteboards, application sharing and file transfer. Microsoft's decision means that applications built on top of its forthcoming Windows 95 operating system can access built-in multipoint-conferencing capabilities.

Microsoft joins a growing list of companies that have decided to detail their T.120 implementation strategies before there are final standards. Others pledging their support in recent months include such suppliers of personal-conferencing software as Avistar (Palo Alto, Calif.), InSoft (Mechanicsburg, Pa.), Picturetel (Danvers, Mass.) and France Telecom North America (New York), as well as services provider AT&T Worldworx. MCI and Sprint have also licensed the only T.120 developers's tool kit, provided by DataBeam.

Arpa to shift focus in its packaging wor k

By Terry Costlow

ARLINGTON, Va. -- A number of the leading packaging engineers will assemble here next week when the Advanced Research Projects Agency (Arpa) hosts a symposium in which the agency will detail its accomplishments in packaging. The assemblage will also hear about Arpa's goals for forthcoming packaging programs and its plans for funding them.

Arpa has invested about $250 million in a number of packaging programs over the past six years. Much of that investment has gone toward building an infrastructure for multichip modules and other advanced packaging schemes, including flip-chip and chip-on-board.

Many of the programs in IC packaging are coming to a close, and Arpa is starting to shift its efforts. Over the next few years, the agency will focus its efforts in a new area.

Nic Naclerio, program manager at Arpa, said, in the future, "our two new areas are mixed-signal packaging and system-level issues. One of the biggest new-focus areas will be in mixed-sig nal MCMs. With wireless taking off, this will be a big area in the future. There are a lot of areas to address: design, test and--on the manufacturing side--we need to look at component reduction."

Sharp ramps up TFT line

By Yoshiko Hara

TENRI, Japan -- Sharp Corp. is ramping up its second Tenri line for production of thin-film-transistor (TFT) liquid-crystal displays and will shift its emphasis to 10.4-inch (diagonal) panels from 8.4-inch displays, according to executives here.

Atsushi Asada, who heads Sharp's display operations, said Sharp plans to open its Mie fab (Taki, Mie prefecture, about a two-hour drive from Tenri) by July. Equipment is being installed at Mie now, and the total investment will reach $530 million. Asada said the substrates at the Mie fab will be large enough to hold nine 10.4-inch panels.

Sharp next month will increase the production rate at the n ew Tenri line to about 60,000 displays per month, with plans to ramp to 130,000 units by September. By March 1996 (the end of fiscal 1995), Sharp predicts, total monthly TFT production capacity at the company will be 460,000 units, of which 150,000 units will be made at the Mie fab.

TSMC mulls fab in West

By David Lammers

HSINCHU CITY, Taiwan -- Taiwan Semiconductor Manufacturing Co. (TSMC), the foundry that helped propel the growth of many fabless-semiconductor companies, is expanding capacity here and pondering the launch of a U.S. or European manufacturing plant capable of 0.25-micron processing.

"We haven't decided yet, but that fifth fab would be the first fab to have a chance of being built outside of Taiwan," said TSMC president Don Brooks. "There are some advantages: right now our customers communicate with our San Jose, [Calif.] office, and then they communicate back h ere to Hsinchu. In the future, customers could have more direct dealings with the factory, and we could have customer-service people right there at the factory."

TSMC chairman Morris Chang, the former TI semiconductor division head who serves TSMC's chairman, said the company recently abandoned talks with AT&T Corp. about using its Orlando facility as the base for a joint-venture foundry. Chang said TSMC now is considering Europe, or the United States.

Five push X-terminal specs

By Michele Clarke

MOUNTAIN VIEW, Calif. -- Five makers of X terminals this month pushed the performance and feature-set boundaries of their low-end lines. Now weighing in at more than 250,000 Xstones, many of these systems will also present more of a workstation look-and-feel with low-memory implementations of the Common Desktop Environment, connect to high-speed networks and house rudimentary mul timedia support.

Topping the performance list are Human Design Systems (King of Prussia, Pa.) and Network Computing Devices (NCD; Mountain View, Calif.). This month, they announced systems that reach 250,000 and 255,000 Xstones, respectively.

The HDS ViewStation Accelerator series includes options for live video and audio with built-in connections for a camera, VCR and TV tuner.

NCD's new HMXpro line is based on the 64-bit Mips R4600 CPU. It has licensed the OpenGL 3-D graphics library from Silicon Graphics Inc.; the systems already support the PEX 3-D extension to Phigs.

Offering 220,000 Xstones, Hewlett-Packard's Envizex "p" series Xstations, announced last week, offer support for the Palo Alto, Calif.-based company's 100VG-AnyLAN networking standard for 100-Mbit/second Ethernet.

IBM unveiled its Xstation 160. Based on a 66-MHz PowerPC 603, the system includes 2 Mbytes of video RAM, expandable to 4 Mbytes, and supports screen resolutions up to 1,600 by 1,280 pixels or to 24-bit color.

In an overhaul of its low end, Sun Microsystems Computer Corp. replaced its SparcClassic and X terminals with redesigned workstation-like models. Both the Sparcstation 4 and the SparcXterminal will use a new pixel accelerator ASIC instead of the company's full-blown low-end graphics acceleration logic.

Flat-panel process eyed for advanced device designs

By Chappell Brown

PORTLAND, Ore. -- A thin-film process called Atomic Layer Epitaxy (ALE), used mainly in flat-panel displays, could offer designers of advanced semiconductor devices unprecedented uniformity over large areas and highly precise control over atomic layer growth. But the benefits of the process have gone largely unnoticed by mainstream semiconductor experts. Now, recent work suggests that adaptations of ALE to semiconductor applications are not only feas ible, but could actually surpass mainstream processes such as chemical vapor deposition (CVD) or high-vacuum molecular beam epitaxy (MBE).

Developed in the late 1970s to build electroluminescent displays, ALE's chief distinguishing property is a built-in chemical mechanism that sets a limit on film growth so that precisely one atomic layer can be defined in each cycle. For materials researchers, this degree of control means that precisely defined structures can be built at the atomic level with a virtual guarantee that the resulting structures satisfy design specifications. ALE also offers high uniformity over large areas and coats all surfaces regardless of orientation_essential factors for advanced superlattice-based devices.

"This is a digital process, which means we can control the deposition of each atomic layer through discrete cycles," explained Raj Solanki, a process expert at the Oregon Graduate Institute, here, "and that has important implications for process control. For example, we can decide on the number of atomic layers we want, enter the data in a control computer, and go home for the day."

Spea prepares low-cost 3-D chip

By Peter Clarke

STARNBERG, Germany -- Spea Software AG, a producer of graphics cards and software, has announced a low-cost 3-D graphics-accelerator chip it is calling T-Rex. The chip is being made in partnership with a major European semiconductor manufacturer, the company said, though executives will not disclose the partner's name until the deal has been completed.

Spea said it intends to bring the graphics performance of workstations, where the company has concentrated its graphics-card business so far, to the PC. The company has its own 3-D applications programming interface (API). Called SP3D, it is a definition of the interface between applications and the way lower-level image- and pixel-manipulation functions are performed by S pea's cards. The Spea 3-D chip has been optimized to support the SP3D API, but it also conforms to other graphics standards such as OpenGL, Hoops and 3DR. Spea believes that will prove useful to its chip-manufacturing partner, which will also be able to sell the chip and derivatives of it.

QuickLogic FPGAs hit 8,000-gate level

By Ron Wilson

SAN JOSE, Calif. -- The QuickLogic FPGA architecture has been driven to a new density level--a nominal 8,000 usable equivalent gates--by QuickLogic Corp. and Cypress Semiconductor Corp. Announced today, the chips preserve the speed, routability and predictability for which the architecture is known, but extend those features into a new density range.

The devices are the result of combining Cypress's 0.65-micron process with QuickLogic's ViaLink antifuse to provide both a fine logic geometry and a very small programmable element. The paired technol ogies lend the chips elemental performance that's quite high, plus enough fast interconnect to deliver that performance at the chip level.

Designated the CY7C387A/388A, the chips contain a 24 by 32 array of logic cells. Each cell in the QuickLogic architecture has a fan-in of 25 signals, which go into various gates, multiplexers and the connections of a D-type flip-flop. Inputs and outputs are unregistered. The chips have an unusually rich complement of routing resources, and 132 (in the 387A) to 172 (in the 388A) bidirectional I/O pins.

SVR recasts IC layout

By Richard Goering

MOUNTAIN VIEW, Calif. -- Silicon Valley Research (SVR), formerly Silvar-Lisco, has introduced what it calls the first combined channel and area IC-layout system. Called SVR SonIC, the tool set is aimed at structured-custom design for such applications as multimedia, microprocessors and microcontrollers.

SonIC employs area-based technology derived from SVR's Gards gate-array product, and channel-based technology from the SC standard-cell product. Added is proprietary technology that links channel-based placement and global routing to area-based final routing. It's the first technology developed since SVR changed its name and most of its management last year.

Area-based technology provides very dense designs and a good engineering change order (ECO) capability, according to T.C. Lee, vice president of engineering. The drawback is that it requires many iterations and doesn't guarantee completion. Channel-based technology offers better completion and turnaround times but doesn't produce optimal die sizes.

"This is really a blend of the two together that will have the die size and density of an area system, and the fast turnaround time and guaranteed completion of a channel-based system," Lee said.

Megatest VLSI tester aims at the next generation

SAN JOSE, Calif. -- Megatest Corp. has rolled out the first member of a new generation of VLSI testers, the Vega Series, aimed at the super-chip performers of the next decade. Model 400, for production and characterization, comes in with a strobe rate of up to 400 MHz and a drive rate of 600 MHz.

To test the new breed of chips, Vega incorporates what Megatest calls the third-generation tester-per-pin architecture as well as a host of timing innovations demanded by the new DSPs, CISC and RISC processors, as well as ASICs. Users can change timing on the fly (period, edge, format), and the new vector-based timing subsystem offers a wide range of event logic sequencing. Vector depth extends to 64 Mbits.

Model 400 comes with as many as 384 pins and two test heaads. Average price is about $9,000/pin.

Taiwan PC makers head toward PowerMac camp

By David Lammers

HSINCHU, Taiwan -- Look for several of Taiwan's high-volume computer makers to wind up in the PowerMac camp. Apple Computer Inc. and the government-run Computer and Communication Research Laboratories (CCL) are negotiating a licensing deal that could be completed by mid-March, said Steven Chen, president of CCL.

CCL engineers would likely work with Apple on PowerMac hardware and software technologies, which would be distributed to several Taiwan-based companies.

Talk of a deal has been in the wind for a long time. Since Apple representatives met with Taiwan partners in June at the Computex computer show here, negotiations have dragged, Chen said. One reason: Apple sought to limit the Taiwan companies' marketing to Asia. That was rejected, so Apple now appears ready to license its System 7 operating system, logic chip set and related technologies.

Meanwhile, Apple has been making inroads elsewhere in Asia. John Floisand, Apple's vice president for Asia, has met with senior managers at Canon Inc. (Tokyo), a PowerPC licensee that wants to move into portable PowerMacs. If Goldstar, Canon and several Taiwan PC makers join the fold, the Cupertino, Calif.-based company could attain its stated goal of 20 percent of the worldwide personal-computer market (it currently holds 12 percent).

In the United States, Radius Inc. and Power Computer signed on with Apple in January, and Pioneer Corp. last week said it will.

HDCD and DVD may come to a resolution soon

By Junko Yoshida and Terry Costlow

SAN FRANCISCO -- Prominent system and software companies are working to head off a war over standards for the next generation of compact disks that would hold the industry hostage to incompatible formats. Executives involved in the discussions say that they're confident a settlement wil l be reached before products come to market.

"They can't go off on another standards war; there are just too many patents involved in this one," says a senior executive of a major U.S. company. The two factions are the Sony Corp.-Philips Electronics partnership, which has proposed the High Density CD (HDCD) format, and the Toshiba Corp.-Time Warner Inc. alliance, which is promoting the Digital Video Disc (DVD).

Indeed, this next-generation CD standoff has shaped up as the biggest standards dispute of the decade, affecting both the consumer-electronics and computer industries. Some industry analysts were anticipating a worst-case scenario under which two incompatible formats could hit the market next year, with DVD becoming the Hollywood-backed movie standard and HDCD supported by system companies. But Philips says that the initial market driver for HDCD will be its use as a storage medium for higher-density CD-ROM data applications.

Meanwhil e, an "informal technology group" comprising IBM, Apple Computer, Compaq Computer and Microsoft reconvened to discuss the issue. The four have been helping Sony and Philips design an HDCD-ROM file-format structure that would maintain backward compatibility with the current ISO 9660 CD-ROM standard. They would prefer adoption of a single, backward-compatible standard serving all industries. The group has no intention of choosing one format over the other, but the four companies had not been approached by the Toshiba-Time Warner alliance and had not reviewed their specifications.

The members of the technology group all have acknowledged their close working relationships with Sony and Philips. Yet, the extent of their public commitment to HDCD has probably fallen short of what Sony and Philips might have expected, especially after a recent Toshiba-Time Warner news conference at which several major Hollywood film studios backed DVD.

More on intellectual property r ights issues.

ISSCC banks on a boom in wireless applications

By Martin Gold

SAN FRANCISCO -- If the International Solid-State Circuits conference was any gauge, the business for chip makers to be in is wireless communications. Nearly a dozen teams of designers descended on the ISSCC to describe the progress they've made in turning large numbers of analog and digital components into highly integrated system chips for wireless systems.

The thrusts for many of the designers were the RF and IF blocks of the popular GSM (Global System for Mobile Communications) digital cellular systems. However, there was also a handful of significant developments in high-performance standalone frequency synthesizer chips, a digital-signal-processor core that will be processed in 0.25-micron CMOS and a very highly integrated voiceband-baseband codec subsystem chip, also for GSM.

Designers used a wi de assortment of processes, including submicron CMOS, high-speed bipolar and BiCMOS. Gallium arsenide is still being employed but only for selected functions, such as power amplifier and RF switches.

"It was not that long ago when many of the radio chips were large numbers of single-function devices. The best that designers have been able to do were a single mixer, a single frequency synthesizer and a single discrete amplifier," says Philip Carrier, marketing manager for wireless-RF products at AT&T Microelectronics (Reading, Pa.). He calls developments like AT&T's single-chip GSM transceiver RF circuit a tremendous design task, explaining that it requires designers with different disciplines. He calls it one of the most highly integrated RF front-end chips for the GSM standard. It was a joint development of AT&T Microelectronics, AT&T Bell Labs (Tokyo) and GP Microdesign (Laureldale, Pa.).

EDA vendors on your team? Cadence, Mentor seek new service model

By Richard Goering

SAN JOSE, Calif. -- If two of the leading electronic-design-automation vendors have their way, the next addition to your design team might just be one of their employees.

Faced with relatively slow growth in software revenue, Cadence Design Systems and Mentor Graphics Corp. are pushing for a new service-oriented business model in which many of the tasks traditionally provided by internal CAD departments are outsourced to EDA companies. Under the new model, EDA vendors would expand their focus beyond software tools and training to provide such services as library development, design-methodology planning, tool selection and even some design-implementation work.

Those who advocate the new model frequently draw parallels to the outsourcing of corporate MIS functions to such companies as Electronic Data Systems (EDS). But competing EDA vendors are understandably wary of their customers' turning to an organization such as Cadence's Spectrum group for internal CAD support.

"What we see from the Cadence Spectrum approach is that it really locks the customer into one single vendor, and you have an obvious conflict of interest," said Alan Labat, senior vice president of field operations at Synopsys Inc. (Mountain View, Calif.).

Dilbert becomes part of the establishment

By Robert Bellinger

Q. What have Martin Marietta CEO Norman Augustine, Rockwell chairman Donald Beall, Tellabs president Michael Birck and an ISDN applications engineer at Pacific Bell named Scott Adams got in common?

A. They all sit on the prestigious National Engineers Week Committee.

But you can bet that Adams is the best known of the group, at least among engineers. For he is the one who makes a living taking potshots at management in his wildly popular "Dilbert" comic strip.

Now seen in more than 400 newspapers around the country, the flat-topped, bespectacled, computer-chained, cubicle-confined Dilbert character has given engineers an exposure to the public that they've rarely enjoyed before.

Of course, there's good exposure and then there's naked-butt exposure. Here's a typical jab: Environmental inspector: "I'm checking the building for environmental hazards. Have you been feeling tired, nervous and disoriented?" Dilbert: "You've just described my entire career."

Bewildered, powerless, swaying before the winds of corporate whims and fancy, Dilbert is whipsawed by managers, human-resources people, lawyers and other forms of ink-ubated life, finding refuge only in front of his display tube.

Adams estimates that 70 percent of his ideas come from readers' e-mail. The other 30 percent of his inspiration comes from his real live engineering job. One reason that the 37-year-old holds onto his day job (he scribbles "Dilbert" off-line) is that he really and truly gets into it--even though he sneaked in through the back door. Adams' title says "engineer," but he only has an economics degree and an MBA.

Still, Adams remains a staunch advocate of engineering. "No field is better," he declares loyally. But one can imagine his fellow National Engineers Week committee members grimacing as Adams goes on to say why: "It's still the most exciting, lucrative job that doesn't involve body parts or police activity."

Actel moves to buy TI's FPGA business

by Brian Fuller

SUNNYVALE, Calif. -- The programmable-logic market went through yet another consolidation last week, as field-programmable-gate-array (FPGA) vendor Actel Corp. agreed to buy Texas Instruments Inc.'s FPGA business.

While the deal has the effect of Actel's buying back the antifuse FPGA technology it had licensed to the Houston-based company seven years ago, it has other ramifications. Actel gets TI's $50 million customer base, giving it a market-share boost, and it gets additional foundry capacity from TI, a manufacturing issue with which fabless Actel has struggled for several years.

The deal--which marks the pullout of yet another large company from the half-billion-dollar FPGA business--also returns the Actel architecture to a sole-source position.

Actel will pay TI $10 million in cash at the deal's close and give TI new preferred stock that can be converted into 2.6 million shares of Actel common stock, which traded when the deal was announced for about $9 a share. That would value the deal at $33 million.

No TI employees will be affected by the deal.

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