EET-i Top of the News

Week of Feb. 13, 1995

Thursday, Feb. 16, 1995

Quiz Intel on its P6, tonight on CompuServe
Microsoft antitrust settlement rejected
Evaluation compares Verilog simulators
Net rats seek games standard
Intel proposes signal processing go native in PC architecture
Graphics chip vendors rushing to software MPEG solutions
What's new(s) at EE Times-interactive

Wednesday, Feb. 15, 1995

Quiz Intel on its P6, Thursday night on CompuServe
Startup seeks market for Sematech CAD tool
Ikos's NSIM accelerator works with Verilog
Teradyne touts vectorless testing
Packaging will be key in U.S. competitiveness

Tuesday, Feb. 14, 1995

3-D TV display takes shape at Photonics '95
Parallel Rambus DSP attacks data-intensive tasks
Rockwell network interface cards hop PCI bus
Over 50 CEOs of Top 100 OEMs hold EE or tech degrees
I-Cube rolls out family of interconnect for ATM and bus switching

Monday, Feb. 13, 1995

ISSCC moves beyond P6
Battle looming over R&D budget request
Synopsys returns to the source
Heads up for high-tech heists
Apple unveils QuickTime conferencing

Quiz Intel on its P6, tonight on CompuServe

Engineer and P6 marketing director Lew Pacely will be available in a conference in the CompuServe Convention Center to answer questions about Intel's successor to the Pentium. Sponsored by EE Times and its EETnet forum on CompuServe, the conference starts at 9 p.m. eastern time on Thursday, Feb. 16, shortly after Intel gives a paper on the chip at the International Solid-State Circuits Conference (ISSCC) in San Francisco. Brian Santo, EE Times 's technology editor and managing editor of EE Times-int eractive, will moderate.

Intel information on the P6.

Microsoft antitrust settlement rejected

By George Leopold

WASHINGTON -- Microsoft Corp. finally met its match this week, when a federal judge here unexpectedly rejected an antitrust settlement as too narrow and toothless.

U.S. District Judge Stanley Sporkin concluded in a 45-page ruling that the agreement between Microsoft and the Department of Justice announced July 15 would not break the software giant's monopoly on personal-computer operating systems or provide an effective remedy for past anticompetitive practices.

"Simply telling a defendant to go forth and sin no more does little or nothing to address the unfair advantage it has already gained," Sporkin wrote. "The decree is too little, too late."

Evaluation compares Verilog simulators

By Richard Goering

FREMONT, Calif. -- The VCS Verilog simulator from Chronologic Simulation Inc. (Los Altos, Calif.) took top ranking in an independent evaluation of Unix-based Verilog simulators by Seva Technologies Inc. The evaluation compared seven simulators and followed earlier Verilog and VHDL comparisons by Seva.

As with last year's evaluation of PC-based Verilog simulators, this year's used a composite "Seva Evaluation Index" (SEI), which weighted such features as performance, language compliance, debugging and design integration. Users can recompute the weightings to come up with their own customized rankings.

The intent is to determine the simulator's overall usefulness, with performance benchmarks as part of a more-comprehensive picture, said Yatin Trivedi, Seva's cofounder.

Simulators compared in the evaluation included VCS, Cadence Verilog-XL Turbo, Intergraph VeriBest Desig ner, Simucad Silos III, CAD Artisans Ausim-VX, Wellspring VeriWell and InterHDL Viper. Verilog-XL Turbo from Cadence Design Systems (San Jose, Calif.), the fastest version of the original Verilog-XL simulator, was ranked second.

Chronologic's VCS simulator won the top SEI score because its run-time performance was roughly twice as fast as Verilog-XL Turbo. Cadence was ahead in all other categories, Trivedi said.

Net rats seek games standard

By Alexander Wolfe

SILVER SPRING, Md. -- "Doom" could be coming to an Internet node near you.

In a proposal now circulating on the Net, a computer-games afficionado is seeking to establish a standard that will enable dozens of players to match wits with each other, in real-time, over TCP/IP connections.

Separately, Id Software (Dallas), the 10-person company that developed Doom, is gearing up to code what's expected to be the first multiuser game on the Internet. Id is also developing a proprietary protocol for the software.

A big impetus for both efforts is the strong interest in multiuser games that's become apparent as the local-area network (LAN) version of Doom has become popular.

The proposal making the rounds on the Internet is in the form of a "working document"--the first step in the long standardization process overseen by the Internet Engineering Task Force (IETF).

The proposal is available via ftp from ds.internic.net , as the file draft-robinson-games-overview-00.txt .

Intel proposes signal processing go native in PC architecture

By Ron Wilson

HILLSBORO, Ore. -- Intel Architecture Labs (IAL) began briefings last week on native signal processing (NSP), IAL's initiative to move many digital-signal-processing (DSP) tasks from dedicated hardware to the personal-comp uter CPU. Far more than a trial balloon, NSP represents a multilateral move by IAL to open a new chapter in the personal-computer architecture. It also poses a direct threat to DSP-chip vendors, which had expected to be major beneficiaries of the multimedia revolution.

Conceptually, NSP is simplicity itself: There is plenty of compute power in a Pentium CPU, so it makes sense to do signal processing on the host rather than on a separate DSP chip. You save money, save complexity and avoid the tangle of incompatible DSP hardware.

But beneath that appealing surface, NSP presents its own serious architectural challenges. The Windows environment in which NSP runs is not a real-time kernel suited to dealing with real-time data flows. The PC bus architecture is not equipped to move data in the manner required for DSP applications. And the Intel CPU chips themselves are not well-suited for DSP computation.

IAL has dealt with each of those problems in turn. The highest-profile action was to remedy the operating-system problem: IAL ported Spectron Microsystems' Spox operating system to the X86 architecture and integrated Spox with Windows so that the Spectron OS can function as a real-time DSP kernel for tasks running on the Pentium.

Graphics chip vendors rushing to software MPEG solutions

By Junko Yoshida

SAN FRANCISCO -- Multimedia-chip and -board vendors are equipping their offerings with software-based MPEG decoding, at little or no cost premium, with an eye toward serving the wave of MPEG-capable personal computers expected by next Christmas. Recent weeks have seen introductions of chips and cards that integrate software MPEG algorithms from Mediamatics Inc., Xing Technology Corp. and CompCore Multimedia Inc.

In the past two days, both Western Digital Corp. (Irvine, Calif.) and Brooktree Corp. (San Diego) announced integration of the Mediamatics (Santa Clara, Calif.) M PEG Arcade Player in their accelerator chips.

Similarly, at the recent Intermedia Conference here, Miro Computer Products Inc. (Palo Alto, Calif.) demonstrated a $179 graphics card that integrates the Xing Technology software-only MPEG Player with an accelerator chip from Alliance Semiconductor. The new board, with no dedicated MPEG-1 ICs, "costs no more than an average graphics-accelerator card," claimed product manager Sean O'Toole at Xing (Arro Grande, Calif.). CompCore (Sunnyvale, Calif.), meanwhile, announced its SoftPEG algorithm at the conference, demonstrating SIF-resolution MPEG playback on a 90-MHz Pentium system with YUV color-space-conversion hardware assist. The company claimed that its algorithm has been ported to a number of basic PowerPC, MIPS and Alpha systems and that it decodes video frames faster than real-time.

Many hardware vendors consider low-cost software MPEG playback the cornerstone of the effort to build an installed base of MPEG-enabled PCs. "By Christmas 1995, we w ill see a big explosion of next-generation multimedia PCs enabled with MPEG playback," promised Thomas Clarkson, division vice president of multimedia marketing at Brooktree.

What's new(s) at EE Times-interactive

For a quick list and links to our most recently posted features, click here .

Quiz Intel on its P6, Thursday night on CompuServe

Engineer and P6 marketing director Lew Pacely will be available in a conference in the CompuServe Convention Center to answer questions about Intel's successor to the Pentium. The conference, sponsored by EE Times and its EETnet forum on CompuServe, begins at 9 p.m. eastern time on Thursday, Feb. 16, shortly after Intel gives a paper on the chip at IS SCC in San Francisco. Brian Santo, EE Times 's technology editor and managing editor of EE Times-interactive, will moderate.

Startup seeks market for Sematech CAD tool

By George Leopold

MELBOURNE, Fla. -- A year-old startup is trying to move computer-aided-design (CAD) software developed by the Sematech manufacturing consortium into the commercial arena as a statistical-simulation package to help designers get a better handle on the large amounts of data generated while monitoring process steps. The data then can be used to fine-tune fabs for production.

Advanced Engineering Technology Inc. (AET), founded here last February, has used the CAD software to develop a manufacturing-process product called Stadium TCAD aimed at design engineers. The new company expects to release a second product later this year focusing on circuit-design applications.

The real-time manufact uring tool is intended to help yield managers automate the monitoring of process steps like oxidation, diffusion and ion implantation by simulating processes, circuits and devices.

Ikos's NSIM accelerator works with Verilog

By Richard Goering

CUPERTINO, Calif. -- Branching out from the VHDL marketplace, Ikos Systems next week will announce Gemini CSX, a simulation solution that links Cadence's Verilog-XL simulator to Ikos's NSIM gate-level accelerator. The integration is provided through a cosimulation link jointly developed by Ikos and Precedence Inc. (Santa Clara, Calif.).

Like its existing Voyager CSX, Gemini CSX is a "mixed-level" environment in which gate-level portions of a design are run on NSIM, while behavioral or register-transfer level (RTL) code is run on a host workstation. While the overall speedup varies greatly according to the mix of gates and RTL, NSIM claims t o run pure gate-level code two or three orders of magnitude faster than a Sparc 10 workstation.

Teradyne touts vectorless testing

By Stan Runyon

WALNUT CREEK, Calif. -- One enigma of automatic testing is how to cut test-program development time while improving fault coverage. Teradyne Inc. claims to have found the solution for in-circuit testing of boards containing SMT devices: eliminate the time-honored test-vector approach.

The vectorless test solution rests in a series of three tools, collectively called the MultiScan set. DeltaScan, WaveScan and FrameScan each attacks a distinct fault class, or set of defects, in manufacturing, though the coverage overlaps.

DeltaScan is an analog junction test that relies on the internal protection diodes found on most pins (usually, to Vcc and ground) of most digital devices, especially CMOS. The object is to uncover defects, especial ly opens, by applying stimulus voltages and measuring the ensuing current differences.

DeltaScan requires no fixtures or sensors, and the test accommodates all packaging approaches, including ball-grid arrays, heat sinks and ground planes. The sole requirement is that unique pin pairs be available on the IC under test to accommodate the stimulus/response methodology.

In operation, as many as six tests are generated for each pin--for repeatability--and all tests must fail for a pin to be indicted. If a pin passes the first test, however, the test software automatically moves to the next pin.

Packaging will be key in U.S. competitiveness

By Ashok Bindra

ATLANTA -- Packaging materials will play a key role in maintaining the U.S. semiconductor industry's lead in the next century, Sematech assembly and packaging director Alex Oscilowski told the first International Symposium on Advanced Packaging Materials this week.

Retaining that advantage, however, will require breakthroughs that can be achieved through close cooperation between national laboratories and universities doing basic research and materials suppliers developing products, he said in his keynote address. Oscilowski said this team effort must be aligned with the Semiconductor Industry Association (SIA) technology road map for semiconductors to make the United States competitive in ICs, electronic assembly and packaging in the next decade.

Industry analysts said that the United States continues to lose share in the worldwide electronics packaging and materials business and that this trend is expected to continue. In a report published by the market-research firm Rose Associates (Los Altos, Calif.), the United States is expected to capture less than 10 percent of the total worldwide market of $6.5 billion for assembly and packaging materials in 1995. Any rebalancing of power will come from a major shif t in technology and new materials, said Bob Clary, vice president of Rose Associates.

3-D TV display takes shape at Photonics '95

By Alexander Wolfe

SAN JOSE, Calif. -- A display that could form the basis for a future three-dimensional television came to light at last week's Photonics West '95 conference. Engineers from the University of Alabama in Huntsville demonstrated ICVision, a prototype that pumps moving holographic-stereogram images through an active-matrix LCD.

"Holograms provide a three-dimensional view but are static," said Jeff Kulick, a codeveloper of ICVision and professor of electrical engineering. "We have gone to the next step by producing a holographic image in real-time with motion."

ICVision is constructed using a 1-inch-diagonal active-matrix LCD from Kopin Corp. (Taunton, Mass.) and a diffractive optica l element for directing light through a series of slits, which form the left and right halves of the stereo image. Each individual frame consists of multiple image slices.

"In a regular hologram, you record a curved wavefront. In ICVision, you record a series of planar images," said Kulick. "The advantage is that the computations required here are greatly reduced, because you're showing a series of two-dimensional graphics images, rather than diffraction gratings."

Parallel Rambus DSP attacks data-intensive tasks

By Chappell Brown

OXFORD, Conn. -- By interfacing Rambus DRAM modules with a unique digital signal-processing chip, Oxford Computer claims to have achieved a price/performance breakthrough in the hotly contested signal-processing market. Rather than simply offering more Mips per dollar, Oxford's A236 chip is claimed to exploit fast-access Rambus technology to eliminate much of the costly system overhead of high-speed cache-memory schemes.

The company has set a third-quarter ship date for a complete DSP/memory system in the form of a small printed-circuit module. The Rambus-based module operates directly on large data sets, making it particularly effective in such applications as image recognition and neural networks, according to Oxford.

Conventional DSP system designs suffer from a double bottleneck: They must buffer incoming data in high-speed memory and then quickly access it over a high-bandwidth I/O system. Both requirements push memory design to its limits, and that translates into high cost.

Oxford's solution is a "small module, about 2 inches square, that contains a high-performance parallel processor, large amounts of DRAM memory and extremely high-bandwidth I/O, all at low cost," said Oxford founder Steve Morton.

The Rambus-memory modules allow the processor to perform direct memory access (DMA) at rates as high as 500 Mbytes/second. Because the processor also supports two 16-bit-wide, 40-Mbyte/s asynchronous DMA ports, the aggregate fast-memory access totals 16 Mbytes of program, data and I/O buffers. That amount of data is available to the processor at an effective RAM-access time of about 3 ns, Morton claimed.

Rockwell network interface cards hop PCI bus

By David Lieberman

SANTA BARBARA, Calif. -- Targeting the PC-server marketplace, Rockwell Network Systems has launched the first in a series of network interface cards (NICs) for the Peripheral Component Interconnect (PCI) bus. The first out of the chute is the Model 2200 Fiber Distributed Data Interface adapter card.

"PCI lends itself well to multimedia and client/server applications requiring dedicated 100-Mbyte/second connections to switches, routers or LAN hubs," said Frank Roys, the company's director of marketing. "PCI servers offer great performance, but that s olves only half the problem. Users still need a high-performance network connection to the backbone to avoid bottlenecks at the server level."

Available in three versions for single-attach fiber, single-attach copper and dual-attach fiber implementations, the 2200 builds on the hardware and software technologies developed for Rockwell's line of VMEbus NICs. The company's Fastracc ASIC design at the heart of the board manages all system-interface and data-movement, -management and -control functions.

Over 50 CEOs of Top 100 OEMs hold EE or tech degrees

By Margaret Ryan

MANHASSET, N.Y. -- A survey of the EE Times Top 100 Systems OEMs finds the majority of those companies are led by chief executive officers or presidents who have engineering, physics or technical degrees.

All together, 100 systems OEMs--deemed by EE Times editors as being early, influential a dopters of technology--were polled. Ten did not respond or could not be reached. Of the remaining respondees, 56 OEMs have technical people at the helm; 34 have chief executive officers who possess other, or no, degrees.

In some cases, such as Rockwell's Donald Beall, the company heads never actually became bench engineers or "techies." In the case of Raytheon, chief executive officer Dennis J. Picard graduated with a business-administration degree but ended up working as an electronics engineer.

The results, presented here as part of National Engineers Week, indicate that engineers, physicists and technical people are not only manning the R&D centers but the board rooms as well.

Engineering-degreed chief executive officers attribute their managerial rise to their engineering background. They said it was learning how to solve complex problems and understanding technology that was most helpful in their everyday jobs.

"Engineering training enables one to approach difficult prob lems without fear," noted Cray Research president and chief operating officer Robert H. Ewald, who holds both a bachelor's degree and a master's degree in civil engineering.

I-Cube rolls out family of interconnect for ATM and bus switching

By Loring Wirbel

SANTA CLARA, Calif. -- I-Cube Inc.'s second generation of programmable-interconnect devices targets a radically different design space from its first product line. The new devices are intended for cost-effective Asynchronous Transfer Mode (ATM) switch design as well as switching for fast system buses like the Peripheral Component Interconnect bus.

The PS (programmable switch) family is being launched with a 48-I/O CMOS device, to be followed in midyear by 96- and 160-port members of the family. The PS family can support a number of data-flow architectures, including flow-through, registered, latched and even analog modes.

The new PS family features a RapidConnect on-chip parallel data bus with a bandwidth of 2.4 Gbits/second. It also allows hierarchical levels of switching--a first for field-programmable interconnect devices. Kent Dahlgren, director of marketing at I-Cube, said that the company wants to work with FPGA vendors on joint designs, and is working with Altera Corp. on an ATM switch and with Xilinx Inc. on a PCI switch.

The internal switching matrix of pass transistors in the device allows one-to-one and one-to-many multicast connections. The PS family defines two levels of switching, controlled by SRAM cells. In the first layer, each SRAM cell controls one switch. In the second layer, an SRAM cell controls an N ý N tile of switches. That way, 4, 8, 16 and other interface data widths can be switched.

ISSCC moves beyond P6

By Ron Wilson

SAN FRANCI SCO -- The Intel P6 CPU may grab the headlines when the doors open today on the International Solid-State Circuits Conference, but the 200-iSPEC microprocessor is just one in a wave of revolutionary currents running through ISSCC.

At 133 MHz and perhaps 200 SPECint92, the P6 is a logical successor to the still-growing Pentium family. But beneath the skin, the P6 is departing from the orthodoxy of superscalar design, as represented by architects at IBM and Sun Microsystems. The microprocessor strives to complete instructions not so much by providing lots of execution units as by keeping a few units from stalling.

Sources said that an analysis of Pentium execution streams led to this strategy. The time lost when a major execution unit stalled, the traces indicated, could not be made up simply by adding further units. Existing X86 code lacks enough opportunities for parallelism.

Breakthrough research is being reported in two areas that will change the way secondary cache is handled. The first is the appearance of extremely fast synchronous SRAMs using wave pipelining. Instead of signals moving through the cache from latch to latch, data is propagated as pulses. The pulses flow through the circuitry in waves timed by phase-locked loops.

Wave pipelining promises enormous frequencies. Hitachi will report on a 4-Mbit CMOS SRAM, built in an experimental 0.25-micron process, that operates at 300 MHz.

But it's not clear what systems designers would use for a cache controller to interact with such chips. One possibility is to substitute wide SRAMs integrated onto the controller chip, instead of synchronous SRAMs with enormous operating frequencies. To that end, Hewlett-Packard Co. will describe a 256-bit-wide, embedded synchronous SRAM array with 1-Mbit capacity, capable of on-chip operation at 295 MHz. It's a 0.35-micron CMOS part.

Demonstrating what can be achieved with 0.4-micron BiCMOS, the ULSI Laboratories at NEC Corp. will unveil a 32-kbit embedded SRAM macro with a 1-ns acces s time.

DRAM designers are threatening to take SRAMs out of the mainstream altogether. That's because as DRAMs get bigger, they are also speeding up. Very fast, wide synchronous DRAMs, working with a sufficiently large primary cache, could make secondary cache unnecessary for most systems.

In ISSCC's DRAM session, Hyundai Electronics will describe a 256-Mbyte DRAM capable of 150-MHz operation. The chip also uses wave pipelining to achieve its high operating frequency.

At 1 Gbit, things just get faster. Hitachi will describe a 1-Gbit experimental synchronous DRAM fabricated in 0.16 micron. Operating at 220 MHz, the chip is faster than most of the next generation of RISC CPUs. Given, again, a sufficiently wide and effective primary cache, such chips could fill and empty cache lines as fast as the CPU could move the data, making secondary caches unnecessary.

Battle looming over R&D budg et request

By George Leopold

WASHINGTON -- In his 1996 budget, President Clinton is challenging congressional critics of federal support for science and technology. He has boosted funding for basic research and government-industry technology partnerships, but the Republicans have vowed to cut those funds in the name of deficit reduction.

A consensus appears to be coalescing in favor of parts of the R&D request, such as sustaining federal support for basic research. However, the administration and House Republicans are expected to clash over funding partnerships that support display, packaging and other electronics technologies. Just how deeply Congress cuts the president's $72.9 billion R&D budget request could be determined by more moderate forces in the Senate, observers said.

"It's in trouble," an industry source said in assessing the prospects for the partnerships. "But the Senate may be keeping a more open mind."

Administration officials overseeing science a nd technology programs stressed during budget briefings last week that the White House is maintaining science and technology as a priority in its $1.61 trillion budget request despite growing pressure to cut discretionary spending. "This budget is focused on harnessing science and technology to solve real problems and create real opportunities," argued presidential science adviser John Gibbons.

Synopsys returns to the source

By Richard Goering

MOUNTAIN VIEW, Calif. -- Proclaiming a fundamental shift in high-level design methodology, Synopsys Inc. last week unveiled the first of a family of "source-level" design-entry and performance-analysis tools. By allowing engineers to stay at the behavioral or register-transfer source levels, the tools promise hardware designers the same types of productivity gains that C source-level development tools have brought to software designers.

Customer reaction was mostly positive, especially for the performance-analysis tools, because users today must go to the gate level to get performance estimates and debug their designs.

The Synopsys announcement followed by one day the introduction of DesignBook by Escalade Corp. (Sunnyvale, Calif.). DesignBook provides design-entry and management tools aimed at facilitating the high-level design process. While the Escalade offering is not directly competitive with the new Synopsys tools, both companies are citing a similar goal: making synthesis-based design easier for existing users and more accessible to potential newcomers.

Synopsys has made available a white paper on the new tools.

Heads up for high-tech heists

By Robert Bellinger

BURLINGTON, Mass. -- "When they show up at your door, there's not much you can do."

"They" are holdup men brandishing 9-mm semiautomatics who plunder parts bins instead of vaults, cache instead of cash.

Once confined to Silicon Valley board-stuffer houses and chip makers, gangs that "steal to order" have gone global. As San Jose Police Sgt. Jim McMahon caustically puts it: High-tech crime is "coming soon to a theater near you": Austin. Long Island. Boston. Singapore. Malaysia. United Kingdom. On the marquee: 486s, hard-disk drives and SIMMs.

In Dallas last year, a gang stormed a Cyrix plant, tied up employees and escaped with $300,000 in chips and other parts.

In Boston, thieves broke into a PC-rental store, pried open the computers and disgorged 486 chips, DRAMs and high-end parts, leaving behind $600,000 in disemboweled laptops, printers and workstations.

In Singapore, armed hijackers picked off disk-laden trucks like duck hunters in a blind.

Crime against high-tech companies is on the rise, and it's spreading from its California origins.

Apple unveils QuickTime conferencing

By Junko Yoshida

SAN FRANCISCO -- Apple Computer Inc. last week unveiled QuickTime Conferencing (QTC), an extension of the Macintosh operating system that enables cross-platform conferencing, collaboration and real-time multimedia communications.

The provision for software-only H.261 videoconferencing on a host PowerPC may threaten the plans of the Personal Conferencing System Working Group, an Intel Corp.-led coalition promoting software-codec specifications based on Intel's proprietary Indeo algorithms.

Apple is not the first company to field software-only conferencing that complies with International Telecommunications Union (ITU) specifications. In the fall, Vivo Software Inc. (Waltham, Mass.) introduced the Vivo320 package, which offers full H.320 conferencing-transmission compliance--including H.261 compression--without the use of dedicated processors.

In addition, videoconferencing-application developers InSoft Inc. (Mechanicsburg, Pa.) and Avistar Systems Inc. (Palo Alto, Calif.) have promised cross-platform codecs. And InSoft has introduced an OpenDVE application programming interface to ease development.

Details on the impending clash between Apple and Insoft.

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