EET-i Top of the News

Week of Feb. 6, 1995

Thursday, Feb. 9, 1995

Loral, Rockwell steer U.S. smart-highway plan
Xpoint, Whitetree tout switch concepts
Circuit-board makers push for European research funds
AMCC offers two 622-Mbit Sonet/ATM families
What's new(s) at EE Times-interactive

Wednesday, Feb. 8, 1995

SGI to acquire application providers Alias, Wavefront
HP revs Unix to support clustering
Cyclone motherboard packs i960
10M-cycle spec for serial EEPROMs

Tuesday, Feb. 7, 1995

Escalade lowers barriers to high-level design
Panel recommends privatization of DOE labs
LSI snares set-top win
Power industry looks to ASC for superconductor expertise

Monday, Feb. 6, 1995

Koreans target logic market
Supercomputers bounce back into spotlight
U.S., Europe to team on strategic ion-beam lithography
New memories melee in frame buffer free-for-all
Digital, ARM, Apple team on next-generation PDA processor

Loral, Rockwell steer U.S. smart-highway plan

By George Leopold

WASHINGTON -- The framework for a national smart-highway system incorporating a range of information technologies will be defined by July 1996 with the Transportation Department's selection of two architecture concepts that will provide the technical basis for standards-setting.

Teams led by Loral Corp.'s Federal Systems Group (Manassas, Va.) and Rockwell's Autonetics Electronic Systems Division (Anaheim, Calif.) have won 18-month "study" contracts to complete architecture development under a public-private partnership called the National Intelligent Transportation System (ITS) program. Rockwell's contract is valued at $4.3 million and Loral's at $3.7 million.

The two teams will work together to define a consensus U.S. architecture compatible around the nation and flexible enough to enable advanced technologies to be integrated into ITS. The U.S. strategy calls for spending more than $20 billion over 20 years to deploy electronics and communications technologies in vehicles and along U.S. highways. An accelerated plan would have the consensus framework in place by the end of 1996.

Xpoint, Whitetree tout switch concepts

By Loring Wirbel

BOCA RATON, Fla. -- Two networking startups last week introduced architectural concepts for bringing low-cost local-area network (LAN) and Asynchronous Transfer Mode (ATM) switching to the desktop. Xpoint Technologies Inc. unveiled a scheme to embed Ethernet switching in a PCI server, and Whitetree Network Technologies Inc. tipped a work-group switch that mixes and matches Ethernet and ATM ports.

Xpoint, a Boca Raton-based Ungermann-Bass Inc. spinoff, took the wraps off a hardware-reference platform called PeerSwitch. Built around an Intel i960 and a PLX Technologies bridge chip, PeerSwitch allows four-port Ethernet switching on a Peripheral Component Interconnect (PCI) card to be embedded directly into a PCI server.

Meanwhile, newcomer Whitetree (Palo Alto, Calif.) gives desktop users a choice of switched 10-Mbit Ethernet or 25-Mbit ATM switching, or a combination of the two, in its WS3000 work-group switch. An expandable stacking bus--similar to a stackable hub but with Sonet connectivity--allows as many as 144 ports to be combined in 622-Mbit links for aggregate bandwidth of 5 Gbits. The WS3000's core price of $7,795 works out to $650 per port.

The two companies are defining a new area in which sub-100-Mbit switched performance may land on the desktop sooner, and less expensively, than analysts had predicted. Whitetree wants to turn ATM switching into a stackable-hub technology, driving low per-port pricing for ATM. Xpoint sees many switching functions moving directly into the server, enabling both work-group dedicated bandwidth and efficient server clustering.

Circuit-board makers push for European research funds

By Peter Clarke

BRUSSELS -- Europe's printed-circuit-board makers are lobbying to ensure they get a share of the European Union's Fourth Framework project, a four-year program that will spend $2.35 billion for information-technology research and development by 1998. The pc-board arm of the Brussels-based European Electronics Components Association (referred to as EECA-PCB) has submitted a proposal called "The Interconnect Density Challenge."

"The European grant system has always favored the semiconductor industry," said Brian Haken, executive director of the U.K.'s Printed Circuit Interconnection Federation, which is represented in the EECA-PCB. "But we have been able to point out that, with annual production worth [$6 billion], the European interconnection industry is considerably larger than the semiconductor side, where production is running at [$4 billion].

"The size and importance of our sector came as something of a surprise to the people in Brusse ls, and when we pointed out that we meet 76 percent of the European market demand while the semiconductor sector meets only 43 percent, they certainly sat up and took note," Haken added.

AMCC offers two 622-Mbit Sonet/ATM families

By Loring Wirbel

SAN DIEGO -- Applied Microcircuits Corp. (AMCC) has introduced two transmitter/receiver chip sets for 622-Mbit networks. The S3017/3018 pair is for Sonet wide-area applications for which loopback and other diagnostics are required; the S3020/3021 pair is intended for all-private Asynchronous Transfer Mode (ATM) switching networks. Both transceiver pairs come in 52-pin, thermally enhanced packages and have per-pair volume prices of less than $100.

Improvements in trench-isolation process technology and thermal-slug packaging have allowed AMCC to cut prices on transceiver pairs while preserving good margins, said Ken Prentiss, network prod ucts marketing manager at AMCC.

As with the original S3005/3006 pair, the two new sets include a full phase-locked loop (PLL) on-chip for clock generation and recovery. They operate from a 5-V supply. The S3017 and S3020 generate a synthesized clock from a slower external reference. They perform the parallel-to-serial conversions prior to output to the Sonet network. The S3018 and S3021 parallelize the incoming data stream, detect Sonet / ATM frames and perform clock recovery through on-chip voltage-controlled oscillation. The two receiver devices have a lock-detect/signal-detect feature to indicate when the PLL is synchronized to the data stream.

What's new(s) at EE Times-interactive

For a quick list and links to our most recently posted features, click here .

SGI to acquire application providers Alias, Wavefront

By Michele Clarke

NEW YORK -- Taking another step away from the industrial-design markets that fueled its rise, Silicon Graphics Inc. (SGI) announced plans yesterday to acquire longtime independent software providers Alias Research Inc. and Wavefront Technologies Inc. SGI said that the complexities of delivering content-creation systems to the entertainment market demand tighter integration between hardware and software suppliers.

Both of the 3-D graphics and animation software houses sell the lion's share of their products on SGI machines and have lines aimed at industrial and entertainment design. Alias has not decided yet whether it will continue to develop its IBM RS/6000 and Apple Macintosh tools after the acquisition, a spokeswoman said, but she said the company was committed to supporting existing users.

The impetus that ignited the acquisitions, according to SGI, is the rise in demand for entertainment content over industrial design. "The design and aerospace markets used to be our most demanding customers," said SGI marketing vice president David Bagshaw. "Today, it's the special effects and entertainment houses like Pacific Data Images, Digital Domain and Industrial Light and Magic. There's such a hardware/software synergy required to serve the entertainment market that our relationship with software providers had to be much more intimate.

HP revs Unix to support clustering

By Michele Clarke and Loring Wirbel

PALO ALTO, Calif. -- The first major upgrade in more than two years of Hewlett-Packard Co.'s Unix operating system, HP-UX, is shipping to key applications software developers. The new OS, HP-UX version 10, introduces a number of features to the PA-RISC platform, including first-time support in software for cluste ring, which is increasingly seen as a key technology for high-end-application server performance.

The system could be in general release as early as midyear, depending on how quickly independent software vendors (ISVs) qualify their packages on the new code. Version 10 includes built-in networking facilities, including bundled Distributed Computing Environment executives and support for Network File System (NFS) 4.2; support for multiprocessing at the workstation level; real-time facilities for the Portable Operating System Interface for Unix; and more APIs to move the operating system closer toward full-spec 1170 compliance.

The company said it expects the operating system to fully comply with the spec 1170 requirements by year's end. "We believe we have 96 to 97 percent of the APIs needed for spec 1170 compliance now," said Guy Provost, product manager for HP-UX on the company's series 700 workstations.

Cyclone motherboard packs i960

By Bernard Cole

NEW HAVEN, Conn. _ Looking to break new ground in the embedded single-board computer (SBC) market, Cyclone Microsystems Inc. is unveiling the first in a series of i960-based motherboards using the Peripheral Component Interconnect (PCI) as its I/O bus.

The SB08 series opens up a new option in embedded computing, said Peter Zacklin, vice president of sales at Cyclone. OEMs traditionally have faced a choice between inexpensive but relatively low-performance motherboards and high-performance but expensive backplane-based platforms.

Embedded PC environments using X86 or Pentium CPUs and ISA/PCI bus offer cost-effective solutions but with severely limited bus bandwidth, Zacklin said. On the other hand, high-end industrial buses, such as VME, offer high performance and the capacity to build large systems but are not cost-sensitive.

Targeting the gap between those options in the embedded SBC market , Cyclone will offer the SB08 in 1,000-piece quantities for less than $1,000 each. The first in the family is the SB08-JF33-102, an eight-slot PCI system board built around a 33-MHz Intel i960 embedded RISC CPU.

10M-cycle spec for serial EEPROMs

By Ron Wilson

CHANDLER, Ariz. -- Microchip Technology Inc. is breaking a psychological barrier in the non-volatile memory business with a new specification that will guarantee 10-million-cycle endurance on many of its most popular serial EEPROM memory chips. The guarantee comes without additional price and is not the result of device screening.

The new endurance level is about 10 times that specified by other serial EEPROM vendors. It is based on 25-degree C, 5-V checkerboard testing.

The higher endurance spec will make it possible to eliminate redundant memory chips, or error-correcting codes, used in many applications that requi re a large number of reads and writes to non-volatile memory. In some cases, it will permit EEPROMs to replace battery-backed SRAM for the first time. Such applications include redial buffers in cellular phones, encryption codes and passwords in GSM telephones and other digital communications devices and parameter memory in some applications.

The new specification is not the result of any one particular change but became possible as a number of incremental changes accumulated, said Microchip director of marketing Thomas Tyson. "We are using a proprietary cell design that we believe to be the industry's smallest, even in our 1.2-micron process. We have a special oxide formula. And we have specially designed charge pumps that don't stress the oxide with sudden changes in voltage," Tyson said. "All these features contribute to greater endurance.

The new specification will be available immediately on Microchip's 24LC family of serial EEPROMs, at densities up to 64 kbits. Other devices will receive th e rating at a later time. There is no additional charge for the new spec.

Escalade lowers barriers to high-level design

By Richard Goering

SUNNYVALE, Calif. -- In a move to bring high-level design automation (HLDA) to rank-and-file engineers, Escalade Corp. this week will announce its widely awaited DesignBook product. Combining elements of electronic system design automation (ESDA) and framework technology, DesignBook promises to simplify synthesis-based design by graphically capturing design intent and managing simulation and synthesis tools.

Escalade's initial thrust is toward the so-called second wave of designers -- those who are starting to consider VHDL and Verilog synthesis. The first product release, available now under Windows 3.1, supports synthesis from Exemplar Logic, VHDL simulation from Model Technology Inc., and Xil inx Inc. placement-and-routing. Escalade developed the product under Windows NT and has established a development partnership with Microsoft Corp.

Product-marketing director Jerry Rau said, "We support the entire high-level design process, from capture of design intent down through simulation and implementation. It's complete methodology support, all the way to silicon."

DesignBook provides register-transfer-level (RTL) design entry through a selection of graphical editors, as well as a VHDL text editor. The editors capture constraints and test vectors as well as functionality. Tool-specific "commanders" then generate optimized code and let users launch and control third-party synthesis, simulation and FPGA-layout tools. FPGA and ASIC libraries will add support for specialized macrocells.

Panel recommends privatization of DOE labs

By George Leopold

WASHINGTON -- The bloated U .S. national laboratories should stick to their core science and engineering missions and be restructured along the lines of a corporate research laboratory, a government advisory board recommends in a report released this month.

The Department of Energy (DOE) task force headed by Motorola chairman Robert Galvin conducted a yearlong study of how the weapon labs should be reorganized to reflect the end of the Cold War and the global technological competition. The panel recommended that "the laboratories be as close to corporatized as is imaginable."

In a two-volume report to Energy Secretary Hazel O'Leary, the task force endorsed transforming 10 of the nation's labs responsible for everything from basic scientific research to nuclear-weapon design into one or several non-profit R&D corporations overseen by a board of trustees. The trustees could include scientists, engineers and industry executives appointed by the president.

"We must begin to evolve, over a period of one or two years, the development and implementation of a new modus operandi of federal support, based on a private-sector style `corporatized' laboratory organization," Galvin said at a meeting here to report the panel's findings to O'Leary.

LSI snares set-top win

By Junko Yoshida

MILPITAS, Calif. -- LSI Logic Corp. insinuated itself into the digital industry's fastest-growing segment--the digital broadcast satellite (DBS) market--by winning a contract from Thomson Consumer Electronics (TCE). It will supply TCE with single-chip solutions for a DBS channel decoder and MPEG-2 audio/video decoder for TCE's second-generation digital satellite set-top box.

LSI Logic will share the MPEG-2 chip slot in TCE's new set-top terminal with SGS-Thomson, TCE's first supplier of MPEG-2 silicon.

TCE's new box--fully compliant with MPEG-2, equipped with a minimum level of interactivity, and 4-bit/pixel col or on-screen-display capability--is scheduled for market launch this summer.

Armed with the industry's first MPEG-2 audio/video system-on-a-chip, LSI Logic hopes to satisfy U.S. consumers' growing appetite for digital satellite systems (DSS), while making deeper inroads in cable and telco set-top markets in both the United States and Europe.

"With many of our design wins in set-top boxes hitting volume in the second half, we expect to see our digital video revenue reach a $100 million run rate in the fourth quarter," said Peng Ang, vice president of LSI Logic's digital video products.

Indeed, with more than 600,000 satellite decoder boxes sold in the first six months since Hughes DirecTV began its DBS service in June, TCE's DSS has become one of the hottest digital video products in the U.S. cosnumer-electronics market. Consequently, booming DSS demand has opened up the single highest-volume U.S. market for MPEG silicon.

It was not LSI Logic but SGS-Thomson Microelectronics who se engineering resource was tapped by TCE to supply two MPEG audio and video chips for TCE's first-generation boxes a year ago. In designing silicon for the second-generation box, however, LSI Logic helped TCE, through its CoreWare program, to meet Hughes' goals for performance, cost and delivery, claimed Ang. As a result, Hughes DirecTV has placed an order with TCE for 1 million second-generation set-top boxes.

Using a 0.5-micron CMOS process technology, LSI Logic's single-chip DBS channel decoder contains four cores: a QPSK demodulator, a Viterbi error-correction core, Reed-Solomon error-correction and a de-interleaver that corrects big bursts of data by first isolating errors in smaller, more manageable segments.

Packing 1 million transistors on a 1-centimeter-square die, LSI Logic's single-chip source decoder integrated MPEG-2 video; MPEG-2 audio (MUSICAM); a customized 62-bit RISC engine for error masking and simultaneous separation of incoming audio and video signals; an audio/video synchr onization; and a programmable graphics controller for on-screen program guides.

Though TCE sponsored development of both chips, LSI Logic has the rights to sell them on the open market, Ang said. He tipped off that the same single-chip MPEG-2 audio/video decoder IC, designated L64002, is in fact going to be used in a set-top box by one of the four Bell Atlantic digital decoder-box suppliers, while it will also be designed into some of the set-top boxes for Canal Plus, a French cable operator that recently announced five set-top-box suppliers, including Sony, Thomson and Philips.

In another high-profile set-top design win, LSI Logic last fall developed a highly integrated single-chip MPEG-2 audio/video decoder for Hewlett-Packard's cable set-top box called the "Kayak" system. Though that chip uses many of the same cores adopted in L64002, such as a customized RISC engine and a programmable graphics controller, it further integrated Dolby AC-3 and DigiCipher video-decoder capabilities in addition to the basic MPEG-2 audio and video-decoder cores.

Power industry looks to ASC for superconductor expertise

By Brian Santo

WESTBOROUGH, Mass. -- The electric-power industry is avidly exploring the potential opportunities provided by high-temperature superconductors (HTS), and at the center of much of the action is American Superconductor Corp. (ASC), an 8-year-old company that invented a way to take brittle HTS materials and spin thousands of meters of wire out of them.

In the most recent announcement, ASC and Asea Brown Boveri (ABB) agreed to develop a transformer made with high-temperature superconductors. The 630-kVA model is intended as a steppingstone to larger, commercial HTS transformers, with the target being 40 mVA.

At the same time, ASC is working with Reliance Electric, the Department of Energy and Electric Power Research Institute (EPRI) to create a 100-hp motor by year's end. (ASC and Reliance have already demonstrated a 5-hp version.) With Southern California Edison and Martin-Marietta, ASC is preparing to demonstrate by the summer the viability of an HTS current limiter, and with Pirelli the company is developing HTS power cables under a contract with EPRI.

Koreans target logic market

By David Lammers

SEOUL, South Korea -- With their memory fabs aging and their product portfolios needing replenishment, Korea's top four electronics companies are preparing to push into the logic side of the business. The four--the Daewoo Group, Goldstar, Hyundai and Samsung--are licensing microprocessor and core-logic cells, and want to acquire or invest in companies with desirable multimedia and telecommunications technology. Meanwhile, the Korean IC makers are building logic fabs and attempting to get more ban g for the buck from their system and logic IC designers.

Of all the Korean firms, Daewoo, a $50 billion conglomerate, may have the most ambitious plans. Company chairman Kim Woo-choong is considering a plan to build a billion-dollar logic fab with a yet-unidentified U.S. partner. Daewoo vice chairman P. June Min has met with U.S. microprocessor vendors in search of advanced process technology that can be licensed. Daewoo is expected to decide this month whether to proceed with the fab.

Goldstar Ltd., the largest maker of consumer products among the Korean quartet, has buttressed its own extensive multimedia efforts by investing in Zenith Electronics, 3DO and other U.S. consumer technology companies. An agreement with Siemens to codevelop microcontrollers was signed last May, and Goldstar Electron is upgrading its Gunmi logic IC fabs for a push in the microcontroller area.

Hyundai Electronics Co. has developed a product focus: one area it has invested in is its work with QualComm Corp. t o understand the logic needs of the digital-cellular data-transmission sector.

At Samsung Electronics the goal is to be a top-10 producer of non-memory ICs by 2005, with $5 billion in annual logic sales. In mid-January, Samsung licensed a consumer-use bipolar process from Toshiba, adding to their joint-development work in NAND-type flash memories and flat-panel driver ICs.

Supercomputers bounce back into spotlight

By Alexander Wolfe

McLEAN, Va. -- Armed with architectural advances that could thrust high-performance computing back into the spotlight, the deans of the supercomputer world are convening here for the IEEE's Fifth Symposium on the Frontiers of Massively Parallel Processing (Frontiers '95).

The industry is pinning its hopes for a resurgence on several developments. At the chip level, what's billed as the first computer to implement multithreading in hardware--via a p roprietary GaAs-based microprocessor--is scheduled to roll out this year. On the systems front, upstart RISC-based parallel processors are for the first time overcoming traditional behemoths in the industry's toughest benchmarks. And software that enables programmers to efficiently divvy up applications for execution on thousand-processor machines is finally taking shape.

In his Frontiers '95 keynote, Burton Smith, chairman and chief scientist of Tera Computer Co. (Seattle), will outline the company's three-pronged effort to squeeze 3-ns cycle times and Gflops-class performance into a machine that's readily scalable to a large number of processors. The solution: build a fine-grained multithreaded architecture, and couple it to shared-memory and high-bandwidth interconnect technology.

As for systems that are available today, there are RISC-based parallel processors built with standardized processor architectures, such as IBM's Power, Digital's Alpha and MIPS's eponymous CPU family.

But ma ny of the most-attended sessions will be those that focus on the industry's longtime stumbling blocks of data-transfer and software-development tools. Some help may come from the Scalable I/O Initiative, which is currently gearing up at a consortium of supercomputer centers and universities. Ken Kennedy, a computer science professor at Rice University (Houston) and conference keynote speaker, is heading a team that's studying software to support parallel I/O. The goal is to present programmers with a shared-memory programming interface. That usually results in more deterministic, or predictable, system performance--an important factor in ensuring that the CPUs in a parallel machine are firing on all cylinders.

This chart from NASA Ames quantifies how traditional supercomputers are being exceeded by parallel RISC-based systems.

U.S., Europe to team on strategi c ion-beam lithography

By Peter Clarke

VIENNA, Austria -- A European consortium is forming in an effort to develop a prototype ion-beam projection lithography stepper, operating at 0.18-micron line widths on 300-mm wafers. The group has pledged cooperation with a related U.S. effort, effectively freezing the Japanese out of the race to commercialize a successor to optical lithography.

"The idea is to have a machine ready for industry by 2000, when 1-Gbit DRAMs will be moving from prototype to volume production," said Max Bayerl, managing director of Ionen Mikrofabrikations Systeme (IMS), the tiny developer of ion-beam projection lithography technology that's leading the European effort.

Joining in the project are European powerhouses SGS-Thomson Microelectronics, Siemens, ASM Lithography, Leica Cambridge, England's Rutherford Appleton Laboratory and the Grenoble submicron silicon initiative (Gressi).

IMS, which has extensive patent coverage of ion-beam projection techniqu es, is also the linchpin in the U.S. Advanced Lithography Group (Columbia, Md.), a consortium formed in August 1993. Members include TI, National Semiconductor, AT&T Bell Labs and the Army Electronic Technology Device Laboratory.

New memories melee in frame buffer free-for-all

By Ron Wilson

SAN MATEO, Calif. -- Half a dozen new dynamic-RAM variants, all armed to the teeth, are converging on one heretofore peaceful spot in the personal-computer architecture: the graphics frame buffer. The result is a major headache for graphics-system designers as they sort through the subtle requirements and bandwidth limitations of each option.

Such main-memory contenders as the extended-data-out (EDO) DRAM, synchronous DRAM and Rambus DRAM are stalking the graphics arena; close behind are new specialty chips, such as window RAMs and MoSys DRAMs. The chips aim to take over the graphics frame buff er as a first step in the greater battle for dominance of main memory. But the aging champions of the frame-buffer contest--the DRAM and video RAM (VRAM)--are not going quietly.

Choosing a frame-buffer memory has traditionally been a straightforward undertaking: DRAM (for low cost) or VRAM (for high performance). Now there are lots of choices--some asynchronous, some synchronous, some single-port, some dual-port, some with built-in graphics features and some without. Each is being touted by its vendors as offering the highest available performance per dollar.

Digital, ARM, Apple team on next-generation PDA processor

By Michele Clarke and Junko Yoshida

HUDSON, Mass. -- Digital Equipment Corp., Advanced RISC Machines Ltd. (ARM) and Apple Computer Inc. will announce on Monday they are codeveloping a family of high-performance, low-power microprocessors based on the 32-bit ARM arch itecture. The partners plan first to turbocharge the Newton PDA and then to flex the so-called StrongArm's Mips in the high end of other embedded-miniRISC markets.

As the newest ARM licensee, Digital brings a 0.35-micron process and high-performance design know-how to a project that technical analysts estimated will produce ARM chips with three to five times the performance of existing versions. From Advanced RISC Machines's perspective, the 100- to 150-Mips CPUs will provide a sorely needed migration path for the architecture that pioneered the miniRISC-CPU category.

Nowhere has the lack of a really fast ARM chip been more apparent than in Apple's Newton. "For higher performance and better handwriting recognition, we can use all the more Mips, but at fewer watts," observed distinguished Apple fellow Steve Capps at the company's Personal Interactive Electronics Division.

Capps acknowledged that the division has been conducting two or three silicon-design efforts in parallel over the pas t several months, including work with Digital on the high-performance ARM processor and with Cirrus Logic Inc. on an unannounced, second-generation PDA chip set.

Free Subscription to EE Times First Name Last Name Company Name Title Email address   Click here for your Free Subscription to EETimes Europe