EET-i Top of the News

Week of Jan. 2, 1995

Thursday, Jan. 5, 1995

Microtec plans Fujitsu support
Radish to sell PBX adapters
ATM net market expected to soar by '98
Fibronics to be a part of Elbit
New tools aid error-correction planning

Wednesday, Jan. 4, 1995

ANSI approves C-plus-plus template library donated by HP
Hitachi wins smart card job
Sony completes PlayStation plan
Synergy moves into broadband
1.8-inch drives in '95? Don't bet on it

Tuesday, Jan. 3, 1995

Ion-beam technique exposes buried treasures
Black holes spawn learning machine
IMPS trims MCM substrate's layer count
AT&T puts voice recognition, answering machine on MCM
DOD helps laid-off engineers into education

Monday, Jan. 2, 1995

Cadence pursues Parsec acquisition
Pentiums without FDIV bug ship to wary market
PC makers start aiming for the living room
Intel, rivalsface off overcommunications specs
Happy New Year!

Microtec plans Fujitsu support

Santa Clara, Calif. -- Fujitsu Microelectronics' MB86930 series of RISC embedded processors has received development tool support from Microtec Research. That company has announced 930 support for the VRTX/OS real-time operating system, the Spectra cross-development backplane and the XRAY source-level debugger.

Microtec's VRTX/OS includes VRTXsa, a kernel that's been ported to the integer unit of the 930 series. Spectra permits debugging of multitasking embedded systems and also provides 930 users with the Xtrace Daemon, a target-resident software monitor. The Xtrace Daemon consumes 30 kbytes and resides on the target, while the host-resident Target Monitor takes over much of the debugging activity.

The Microtec tools provide an easy upgrade path for users of CISC processors, said Sue Lubais, director of marketing for the Fujitsu 930 Series. The development kit starts at $4,950 per seat.

Radish to sell PBX adapters

Boulder, Colo. -- Radish Communications Systems Inc., which had backed out of most character-display hardware production in favor of licensing its VoiceView software protocols for switched voice and data over analog lines, is moving back into hardware with the 1995 introduction of InsideLine. The device is a Y adapter that connects a telephone handset and base to allow VoiceView-quality modem transmission behind PBX systems, such as those in hotel rooms and large office complexes.

Paul Davoust, Radish vice president of marketing, said the device was developed internally to broaden the appeal of the VoiceView protocols for remote-access applications. The $120 product can be used with VoiceView-certified modems to allow data and fax display connections from remote PBX lines. Radish will sell InsideLine through direct mail channels.

ATM net market expected to soar by '98

San Jose, Calif. -- The U.S. market for ATM networking products is still in its infancy, but it is expected to reach mammoth proportions by 1998, according to a report from Electronic Trend Publications.

In the most recent figures, U.S. sales for ATM LAN products totaled $23.3 million, according to the report. But projections indicate the U.S. market will experience a compound annual growth rate of 150 percent to $2.4 billion in ATM LAN product revenues by 1998.

Videoconferencing and other new bandwidth-hungry applications will drive ATM growth.

Fibronics to be a part of Elbit

Haifa, Israel -- Elbit Ltd. has acquired all assets of Fibronics International Inc., an internetworking company with headquarters in Pembroke, Mass., and an R &D center in Haifa. Each share of Fibronics stock was exchanged for 1/20 share of Elbit ordinary shares. Elbit issued 406,127 shares of stock to cover the transaction, which was completed Dec. 30, making Fibronics a subsidiary of Elbit.

Fibronics, founded in 1977, had been an early player in fiber-based systems such as fiber multiplexers and FDDI LANs. It had recently expanded into gigabit switching hubs based on FDDI backbones. Elbit, a communications and DSP specialist with a background in military communications and intelligence projects, has been looking for ways to diversify into commercial markets, particularly those serving multimedia communications.

New tools aid error-correction planning

Menlo Park, Calif. -- A new generation of channel-error measurement and error-correction tools is coming to the aid of beleaguered systems designers. In systems from disk drives to ATM networks, eng ineers are increasingly forced to rely on forward-error-correction (FEC) techniques. But such algorithms must be tuned to the specific noise characteristics of the channel involved. Rough statistics like bit-error rate are of little use in setting the right parameters. New tools specifically designed for the tuning of FEC can help.

Two San Francisco Bay Area firms are supplying two very different pieces of hardware to meet this need. One, from SyntheSys Research Inc. here, records and characterizes errors in the channel for later analysis. The other, from Kodak Berkeley Research (Berkeley, Calif.) is a programmable Reed-Solomon engine that can be used to prototype error-correction systems.

A fundamental step in selecting an error-management strategy, according to SyntheSys vice president Jim Waschura, is to determine the characteristics of the errors a channel presents. Are there only isolated single-bit errors? If not, how long are the error bursts? Are they data-dependent?

"Designers get real ly frustrated with traditional bit error rate measurements, because they don't give the kind of information you need," Waschura said. "It is essential to record not just the error rate but the positions of the errors in the data stream. Only with that information can you make good decisions about block lengths and correction schemes."

To meet this need, SyntheSys developed a unique channel tester. The device generates data blocks, either from random patterns, pre-programmed patterns or user-defined patterns. It then compares the transmitted data with the received data, recording the positions of the errors. An embedded personal computer within the box can then present the error data as locations, burst-length histograms or other displays. The user interface is a touch-sensitive flat-panel display.

In addition, the box includes error-correction simulation software. Working with the error-position data, users can specify the number of correction bytes per block, interleaving techniques and other param eters to the simulator, and see the effect such a correction scheme would have on the errors.

Simulating error-correction off-line, after the data has been sent through the channel, can have some important benefits. For one, Waschura said,"This can be very helpful when you have only limited access to the channel." Designers can connect to the channel for a brief period, send their data patterns through, record the error characteristics and retreat to analyze the data at their leisure.

ANSI approves C-plus-plus template library donated by HP

By Loring Wirbel

Palo Alto, Calif. -- A Standard Template Library (STL), developed at Hewlett-Packard Labs as an extension to the C-plus-plus object-oriented language, has been approved by the joint standards committee of the American National Standards Institute and the International Standard s Organization. One of the library's developers said it could increase the language's popularity while making it easier to use.

HP Labs research manager Alexander Stepanov, who developed STL with HP Labs' Meng Lee, said that widespread use of STL in compilers and development tools "should hasten the move from C to C-plus-plus by many programmers, since it simplifies use of C-plus-plus significantly."

Final approval of STL is linked to the move of C-plus-plus itself from draft to final standard, expected to take place early this year. STL defines a broad set of algorithms for manipulating data structures through sorts, merges, transforms and similar operations. The full STL standard, comprising a 70-page extension to the ANSI/ISO C-plus-plus standard, defines programming guidelines and generic, predefined software modules for implementing operations.

Hitachi wins smart card job

By Peter Clarke

London -- When electronic cash smart cards are introduced in the U.K. next July, Mondex will embed a customized version of the Hitachi H8/310 microcontroller in a card it sees as its key to becoming a global player in the bankcard industry.

Mondex was formed in 1990 by NatWest Bank, one of the U.K.'s leading banks. But Mondex will operate like Visa or Mastercard: banks that take on a local Mondex franchise will buy into the national organization as well as Mondex International, the global body responsible for standards. Already signed up is the Hong Kong and Shanghai Bank, which has acquired franchises for 10 Asian countries including Singapore, Taiwan, India and China.

"Hitachi will be working with us on the next stage of the development to provide an advanced technical platform for the wider introduction of Mondex starting in 1996," said Tim Jones, chief executive officer of Mondex.

David Morton, a spokesman for Mondex, said, "The development of Mondex will probably necessitate licensing of European manufacturers of the chip; and similarly in the U.S. But Hitachi are in the lead."

Sony completes PlayStation plan

London -- Sony has formed Sony Computer Entertainment (Europe) to complete its preparations for the worldwide introduction of the PlayStation, its 32-bit CD-based video game system. The company will have European responsibility for sales of the PlayStation. Sony Computer Entertainment of America was set up to oversee U.S. sales.

Chris Deering, formerly executive vice president of Sony's Columbia Tristar Home Video International, has been named president of the new firm.

The PlayStation was launched in Japan in December 1994 and will be released in Europe and the United States in 1995.

Synergy moves into broadband

By Loring Wirbel

Santa Clara, Calif. -- Synergy Semiconductor Corp. is making its first foray into broadband communication products, using its trench-isolated Asset (All Spacer Separated Element Transistor) emitter-coupled logice (ECL) process to develop a single-chip transceiver for 622-Mbit/second Sonet/Asynchronous Transfer Mode applications.

Raj Patel, director of business development at the ECL/BiCMOS specialist, said that Synergy wants to apply high-speed bipolar design talents to mixed-signal circuits and complex broadband communication products.

The 622-Mbit Sonet rate known as OC-12 represents a good starting point for Synergy, since 155-Mbit OC-3 rates have been heavily exploited by many CMOS product specialists. This does not mean, however, that 500 Mbits will be the slowest ATM/Sonet realm explored by Synergy. Patel said that the company has several concepts to examine involving multichannel transceiver design and adaptive equalization for copper twisted-pair wiring, wh ich may provide the impetus for offering 155-Mbit transceiver parts.

"There is no sense offering something which can be implemented just as easily in CMOS. We started at OC-12 because we think that CMOS will begin to lose steam around 150 MHz," Patel said. Synergy sees its 1.2-micron Asset process technology as capable of supporting speeds to 3 GHz.

1.8-inch drives in '95? Don't bet on it

By Terry Costlow

Chicago -- The 1.8-inch-drive market has had three years of disappointing sales, and industry analysts are split over whether they are in for a fourth. Industry watchers predict continued good growth for 2.5-inch drives, but 3.5-inch models will dominate the industry, with shipments growing by more than the total of the two smaller form factors put together.

One of the big questions in the disk-drive market is when 1.8-inch-drive sales will crack the million-unit level. Pr ognosticators said it would happen in 1992, pushed that back to 1993, then to 1994. Last year, optimistic researchers say shipments didn't hit 500,000, and others are far less bullish.

"I wish I could say that this will be the breakout year for 1.8s, but that doesn't appear to be in the cards," said Mark Geenen, president of TrendFocus (Palo Alto, Calif.). "There will be strong demand, but I don't feel it will go to 1 or 2 million. It looks like last year was limited to 150,000 or 250,000."

Ion-beam technique exposes buried treasures

By Ron Wilson

Hillsboro, Ore. -- A new micromachining technique developed by focused-ion-beam experts at FEI Co. promises to lay open the secrets of circuit nodes buried beneath metal layers on multilayer metal ICs. The approach deposits insulating material under control of the ion beam, making it poss ible to create an insulated contact that passes through metal layers on its way to a buried node.

The technique also could be used to build multilayer metal structures, to replanarize excavated areas of a chip or to repassivate chips after focused-ion-beam operations, according to FEI.

The process involves flooding the chamber of a focused-ion-beam (FIB) system with a carefully selected gas, according to FEI applications development manager Jay Lindquist. FEI would not reveal the composition of the gas, since patents are being sought. The gas is introduced to the chamber at relatively low pressure--much less than that present in an ion etcher--so it does not interact by itself with the surface of the IC placed in the chamber.

Once the gas is introduced, a controlled-energy ion beam is focused on the IC. At the point at which the beam strikes the surface of the chip, it causes the gas to decompose, depositing a form of silicon oxide on the surface. By controlling the beam motion, the oxide may be built up in virtually any desired pattern, Lindquist said.

Black holes spawn learning machine

By R. Colin Johnson

San Francisco -- Black holes have provided inspiration for an entirely unexpected application outside of astronomy. Black Holes, an add-on to Gray Matter Tech Inc.'s Brain Chaos real-time simulator, stores information in an architecture that extends the realm of Einstein's relativity principles to recognition, simulation and prediction.

Within the add-on, synapses are referred to as black holes, and learning is analogous to determination of the relativistic force of gravity between free bodies. That contrasts with the conventional neural-learning method of finding the lowest point on an energy landscape, in a process analogous to Newtonian gravity.

The Black Holes learning module harnesses the mathematics of black holes to create a network of associative m emory locations. Gray Matter's architecture consists of a spatially separated network of black holes that each represent a specific input/output pair in the training database.

Inputs within the architecture are encoded as the location of a point in its space/time continuum; outputs are represented by the curvature of the space/time continuum at that point. Learning is performed by modifying the strengths of the "gravitational fields" at each black hole by increasing or decreasing its "mass" until the correct output is obtained.

IMPS trims MCM substrate's layer count

By Terry Costlow

Fayetteville, Ark. -- Researchers at the University of Arkansas have devised a new technique for interconnecting circuits on a multichip module, reducing even very high-density substrates to two layers. The interconnected mesh power system (IMPS) holds enough promise that MCM maker Nchip Inc. is evalua ting it as a way to reduce costs.

Researchers at the university's High-Density Electronics Center who developed the design topology said it can reduce substrate costs by more than half over common techniques that require four or five layers. Despite using only two layers, the IMPS technique provides controlled impedance and low crosstalk levels. The technology will be detailed at the IEEE's Multichip Module Conference in Santa Cruz, Calif., Jan. 31 to Feb. 2.

The IMPS technique combines power, ground and signal lines in each of the planes, with one plane holding east-west lines and the other consisting of north-south traces. Signal layers are thin strips that are sandwiched by larger power and/or ground lines.

AT&T puts voice recognition, answering machine on MCM

By Terry Costlow

Santa Cruz, Calif. -- Now that the size and speed requirements for some circuits are manda ting the use of multichip-module technology, designers are finding that MCMs can shrink another important parameter: time-to-market. AT&T and Altera Corp. will describe how their forays into MCMs have reduced their cycle times when the IEEE's Multichip Module Conference convenes here Jan. 31 to Feb. 2.

The AT&T module provides voice recognition combined with a cellular-phone answering device (VR/TAD). It houses mixed technologies, and since the chips all have support tools, the need for simulation is minimized. The DSP, microcontroller and ROM all have mask-encoded firmware, so use of existing chips and tools makes production of that firmware much easier than developing code for use with an ASIC. Overall, the design and fabrication cycle spanned 13 weeks from schematic preparation through assembly and test. The VR/TAD in use today is implemented on a board that weighs 32 grams and measures 6.7 square inches. The MCM alternative puts nearly all the parts on a substrate that weighs only 2.3 gram s and consumes about 1 square inch of board space.

Meanwhile, Altera put four 12,500-gate PLDs and a programmable-interconnect chip on a ceramic substrate to create a 50,000-gate PLD. That creates a PLD large enough to verify gate-array designs using silicon that can run the same source code that will be used with the gate array.

DOD helps laid-off engineers into education

By Robert Bellinger

Irvine, Calif. -- Under a $5 million Defense Department program, 20 laid-off defense and aerospace scientists and engineers will be retrained to teach math and science at inner-city Los Angeles-area schools.

"They could bring so much reality into the classroom," said director Maureen Shiflett of the industry engineers and scientists. "If they're teaching algebra, they'd be able to tell middle school and high school students, `this is how we used it,' " said Shiflett, director of the Nati onal Research Council's education programs in the West.

The pilot program has two aims: to tap the talents of engineers and scientists furloughed from contractors, government labs and aerospace firms in Southern California, and to fill "a crying need" for math and science teachers in the Los Angeles Unified School District.

"There are plenty of openings," said Shiflett. The school district estimates it has 60 to 70 positions in middle and high schools. Responding to criticism that retraining programs in the past haven't led to jobs, Shiflett said, "We can't offer an absolute guarantee, but the jobs are there. But candidates must be willing to teach where the jobs are."

Cadence pursues Parsec acquisition

By Richard Goering

SAN JOSE, CALIF. -- Cadence Design Systems is going to acquire Parsec Software, the Los Altos, Calif.-based maker of the Pearl timing analyzer. Cadence's objective: access to the timing-analysis capabilities at the heart of deep-submicron-design performance.

The deal, for which Cadence last week signed a letter of intent, would help Cadence formulate a methodology to enhance sub-half-micron, timing-driven designs --where interconnect delays are starting to dominate gate delays-- as well as regain lost ground in the timing analysis market. Though the acquisition, expected to be completed early in the new year, could put Cadence in a more competitive position with Epic Design Technology (Santa Clara, Calif.), the real motivation is much broader, said Cadence president and CEO Joe Costello.

Parsec's Pearl analyzer is one of the few available that can handle both transistor- and gate-level design. As such, it poses a competitive threat to Epic's PathMill, which has gone virtually unchallenged in the transistor-level timing-analysis market.

"Our intent is not to compete with a parti cular timing solution," Costello said. "Our intent is to build this technology into a number of our solutions. That's why we acquired Parsec, as opposed to having an arm's-length relationship."

Pentiums without FDIV bug ship to wary market

By Ron Wilson

SANTA CLARA, CALIF. -- The noise from media circus surrounding the floating-point bug in Intel Corp.'s Pentium CPUs is subsiding, but the after-effects linger on. And they will be felt long into 1995, influencing not just Intel but its customers, competitors and even software vendors.

Through the first quarter, the most visible effects will be on Intel itself. Since the company announced that it would exchange Pentium CPUs on a no-questions-asked basis, a significant portion of Intel's manufacturing resources has been diverted to replacement, rather than new-product, shipments. Demand is reportedly very strong.

This puts stress no t only on Intel's 800-number phone center but also its manufacturing plants. The new steppings of the Pentium P5 and P54C chips are just going into production and no wafers are being started with the old masks. But huge numbers of wafers stepped from the old mask sets are still in process. Intel sources said that nearly half of the company's Pentium output in the first quarter will be the old stepping. Since Intel clearly must send new-version chips to the replacement customers, it will still be shipping to OEMs large numbers of chips carrying the bug.

More significant than the manufacturing issues may be the sensitivity of customers to discrepancies in the Pentium hardware. For starters, Intel is probably not through having problems with the Pentium. Independent testing laboratories say Pentium is going through a normal evolution, which means the chips are still likely to have an ample supply of so-called bugs to be uncovered.

Many of these problems are of interest only to validation engineers, occurring at corner conditions of addressing modes, data types, power and temperature. Some involve hardware that will be used only in multiprocessing. Intel sources admit that there are several such known errata in the new steppings of the chips. But as Windows 95 and 32-bit Windows applications begin to appear, presumably this year, some of the heretofore innocuous discrepancies may take on new meanings. This process has unfolded for virtually every new CPU introduced in recent years.

PC makers start aiming for the living room

By Junko Yoshida

FREMONT, CALIF. -- Manufacturers of personal computers are threatening to turn upside down the turf battle between PC and TV for dominance as the home multimedia-platform of choice. Their weapons are $500 set-top PCs specifically designed to hook up to televisions.

These second PCs at home won't come with a VGA monitor but will have a CD-ROM d rive, primarily for playback of CD-ROM-based multimedia titles and PC video games on large-screen TVs. High-end models may also be able to receive on-line services via the TV or connect with other PCs in a household to build a home network.

Betting big on the nascent market are graphics-chip vendors Cirrus Logic Inc. (Fremont) and S3 Inc. (Santa Clara, Calif.). Both plan first-quarter introductions of chips that will bridge the gap between desktop-PC and consumer set-top graphics.

Cirrus Logic will take the first stab with a true-color VGA-graphics controller integrated with TV processing for output. Designated the CL-GD5425 and priced at $20 in volume, the Cirrus chip features a glueless interface to a low-cost NTSC/PAL encoder to deliver high-quality graphics and video via the TV screen.

S3, meanwhile, plans a first-quarter introduction for devices based on what it calls an entertainment-acceleration architecture. "The new architecture will respond to highly demanding home-PC requirements such as simultaneous acceleration of 3-D movie and 2-D graphics, and it goes right onto a motherboard," said strategic marketing director Kanwar Chadha. S3 is keeping the details of its architecture under wraps, but Chadha said that 3-D graphics and video are baseline features.

Intel, rivalsface off overcommunications specs

By Michele Clarke

HILLSBORO, ORE. -- With no less at stake than who decides how data, voice and, ultimately, motion video will move between telephone lines and applications software, Intel Architecture Labs and computer-telephony initiative Versit are competing to define a new computer-communications architecture by summer. Each hopes to present a sufficiently impressive list of specifications, standards and big-name implementation agreements to convince system architects to adopt its conventions.

Ironically, both appear to be converging on the same macro-architectu re. At the physical layer will be a moderate-speed (2- to 5-Mbit/second) serial bus for isochronous data. That has long been on the wish list of OEMs seeking to integrate voice recognition and phone-based voicemail into telephony-application software.

Above the serial link will lie layers of format and application-programming interface (API) specifications that will make the various forms of data available to application programs on the PC.

But from the serial link to the API, the two camps seem virtually committed to incompatibility.

Happy New Year!

The staff of EE Times and EET-i wish you a happy, healthy, and prosperous 1995!

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