EET-i Top of the News

Week of Dec. 5, 1994

Thursday, Dec. 8, 1994

ATM Forum to Consider 25-Mbit Proposals
Motorola upgrades French wafer fab
HP acquires software firm
Games machines hit jackpot
Shimadzu spins a blue laser
Alcatel in WAN deal with Micom

Wednesday, Dec. 7, 1994

Compass, Synopsys forging tool links
Digital video, data storage get Commerce funding
More Megatest's woes: revenue cut in half
National may pass industry average
Compaq sees growth in consumer niche
Intergraph wins Seiko order

Tuesday, Dec. 6, 1994

Compaq eyes fix for Pentium glitch
MRS meeting reveals future of electronics to be broad and deep
ISA moves into 3-D MCMs
Destiny compresses printer images
Viewlogic updates PRO Series

Monday, Dec. 5, 1994

Intel's Pentium parry: revised CPUs begin to appear
Jedec set to approve very-high-speed I/O spec: HSTL
HSTL and TTL's other would-be successors
The coming convergence crawl
Pipelined SRAM becomes a Pentium bottleneck
How pipelining saves the day
Wireless world eyes Europe's GSM spec
NTT pledges fiber to home by end of decade

ATM Forum to Consider 25-Mbit Proposals

By Loring Wirbel

Kyoto, Japan -- The ATM Forum has taken what could be a giant step toward a lower-speed Asynchronous Transfer Mode stan dard. At a meeting here earlier this month, the standards body voted to consider two competing proposals for 25-Mbit/second ATM user/network-interface physical layers.

The forum will consider the proposals at a February meeting in Burlingame, Calif. The competing proposals come from the Desktop ATM25 Alliance, an IBM-led group that touts a 25.6-Mbit/s interface, and the Uni-Phy alliance, led by PMC-Sierra Inc., which promotes a 25.9-Mbit/s standard.

The ATM Forum voting process revealed some intriguing power blocs, according to industry sources. Apple Computer Inc., Novell Inc., Microsoft Corp. and 3Com Corp. joined the members of the Desktop Alliance in urging that at least some 25-Mbit proposals be considered. Indeed, an Apple representative made a strong plea for the necessity of 25-Mbit ATM.

One computer-industry source suggested that Apple and IBM may wish to roll a 25-Mbit ATM standard into the Versit suite of proposed communication standards, in which both vendors are involved (s ee EE Times , Dec. 5, page 2).

But the regional Bell operating companies are largely opposed to the 25-Mbit proposals. Most of the RBOCs are planning video-dialtone interfaces at the standard ATM rate of 51.8 Mbits/s and thus require a desktop market at that speed if they are to amortize equipment costs.

Motorola upgrades French wafer fab

Toulouse, France -- Motorola Inc. will spend $140 million to expand production at its wafer fab and open an R&D center here. The plant makes analog, mixed-signal, smart-power and RF ICs, plus optoelectronic devices and discrete power transistors.

Motorola will spend about $110 million to triple the capacity of smart-power chips over the next two years. That comes on top of a $50 million investment made in 1993. Money will also be spent on a new R&D center, to be built in conjunction with the local university and national research la b, that will develop smart-power IC technology and sensors.

HP acquires software firm

Palo Alto, Calif. -- Hewlett-Packard Belgium has acquired Alphabit, a seven-person company in Ghent, Belgium, that develops electromagnetic simulation software. Alphabit's technology will be used to enhance the HP EEsof line of high-frequency design tools.

Following the acquisition, Alphabit employees will be integrated into HP Belgium's organization and will contribute technically to HP EEsof. HP worked with Alphabit before the acquisition, and owned 16 percent of the company. Terms of the acquisition were not disclosed.

Alphabit was founded in 1992. Co-founder Paul Lagasse is director of the department of information technology (Intec) at the University of Ghent, and a recognized expert in high-frequency electromagnetic technology. HP will maintain the operation in Belgium and continue t o work closely with Intec.

Games machines hit jackpot

Tokyo -- Sony Computer Entertainment and Sega Enterprises have each reported first-day sellouts for their new 32-bit game machines. Sony said it sold 100,000 of its $400 PlayStations on the first day of sales. Sega sold 170,000 units of its $450 SegaSaturn game system on its debut date early last month and another 80,000 units over the final days of November, said a Sega spokesman.

Sega claims that it has received orders for 1.4 million units from wholesalers, and the current production capacity will not satisfy demand. Hitachi Ltd., which makes the SH-series CPU and other components used in the SegaSaturn, will also make the game system on an OEM basis at subsidiary Tokai Electronic Co.

Shimadzu spins a blue laser

Kyoto - - Shimadzu Corp. has developed a 473-nm solid-state second-harmonic-generation blue laser that is both compact and has a semi-permanent life.

"These are big advantages over gas lasers, which are large, expensive and short-lived," said a Shimadzu spokesman. The laser will hit the market next month.

Researchers working at Shimadzu, which is a precision machinery manufacturer, last July revealed that they had succeeded in building a second-harmonic-generation laser that emits 473-nm blue light continuously at room temperature, consuming 32 mW. The system is based on an 808-nm lasing engine.

They subsequently redesigned the structure of the optical resonance unit so that the Nd:YAG crystal generates a basic light wave of 946-nm light. That made it possible to reduce the noise level from -100 dB/Hz to -140 dB/Hz.

Alcatel in WAN deal with Micom

Paris -- Alcatel Business Systems last week signed a global distribution pact with Micom Communications Corp. (Simi Valley, Calif.). Developer of such wide-area-network access products as the Marathon and NetRunner series, Micom has been winning new converts to a low-speed cell-switching concept it calls Microband ATM. Alcatel will have worldwide rights to combine Micom platforms with its own line of integrated voice/data hubs and PBXs.

Compass, Synopsys forging tool links

By Richard Goering

San Jose, Calif. -- Bolstering its deep-submicron support, Compass Design Automation has announced that it is working with Synopsys Inc. (Mountain View, Calif.) to link Synopsys synthesis tools to Compass's ChipPlanner floor planner. Compass has also disclosed a new version of ChipPlanner with new libraries and enhanced timing-driven support.

Linking synthesis with layou t is critical for deep-submicron designs because wiring delays have a huge impact on timing. Through a utility called Floorplan Manager, Synopsys has previously announced two-way ties to floor planning or layout tools from ArcSys, High Level Design Systems, LSI Logic and Texas Instruments. Synopsys's work with Compass is similar to those agreements.

As of today, Compass customers can bring in Synopsys synthesis data and write a script file to convert floor-planning information back into Synopsys's format. The work between Compass and Synopsys will automate that process, according to Jeff Lewis, director of corporate marketing at Compass.

Specifically, Compass will support Floorplan Manager in the second quarter of 1995. After bringing in synthesis data from that utility, ChipPlanner will output geometric data using the Physical Design Exchange Format (PDEF) and timing data using the Standard Delay Format (SDF). That information can be brought back into FloorPlan Manager, which reoptimizes the design to meet timing constraints.

Meanwhile, a new version of ChipPlanner, available in early 1995, will provide timing-driven, path-oriented placement. That will help the tool meet constraints established in Synopsys's Design Compiler. In addition, the new V8R4.7 release adds clock-tree optimization, which makes it possible to reduce skew.

New ASIC libraries available with ChipPlanner include 0.8-micron gate-array libraries from Mitsubishi and American Microsystems Inc. A vendor-independent tool, ChipPlanner is also supported by Toshiba, VLSI Technology, Hitachi, Hyundai, Goldstar, TSMC and Matra-Harris. ChipPlanner starts at $40,000 on Unix platforms.

Digital video, data storage get Commerce funding

By George Leopold

Washington -- Two five-year programs focusing on digital video and data storage are among six new technology areas to be pursued under the Commerce De partment's Advanced Technology Program, the department's National Institute of Standards and Technology (NIST) has announced.

A $125 million digital data storage program will concentrate on six technical objectives: increased tape and disk storage density, better magnetic recording heads, new lubricants and surface finishes, more reliable tracking devices, improved signal processing and advancing the state-of-the-art in data storage and retrieval software.

The second effort, called digital video in information networks, will commit $120 million to develop interoperable digital video capabilities for emerging information networks. The projects will focus on techniques for encoding, converting and transcribing video data into forms required by emerging networks.

There was no word last week on when NIST will begin seeking proposals for the focused technology project.

More Megate st's woes: revenue cut in half

By Brian Fuller

San Jose, Calif. -- Citing stalled orders, ATE vendor Megatest Corp. last week said that its 1995 fiscal first-quarter revenue will plummet by more than 50 percent from the previous quarter.

In a second dour financial announcement in a month, Megatest officials said revenue for the period ended Nov. 26 is "expected to be in the range of $12 million." That's down from $22.4 million for the year-ago period and $27.5 million for the fourth quarter of 1994.

The sales decline could result in an operating loss of $4 million, officials said.

In addition, Megatest will incur a non-operating charge related to its acquisition of the 1149 Tester product line from Micro Component Technology Inc. Final financial results for the first quarter will be reported later this month.

"As we have previously indicated, our major memory and logic customers have delayed placing new orders, as they continue to evaluate their needs," said J ohn E. Halter, Megatest's chairman and chief executive officer. Halter noted that the company will cut costs quickly if the sales slowdown continues.

National may pass industry average

San Francisco -- National Semiconductor Corp. chief executive officer Gilbert Amelio last week offered another bullish outlook for his company, telling an investors' conference here that the company will outgrow the semiconductor industry average in two years.

Amelio said the semiconductor market is forecast to grow 14 to 15 percent in 1995, and National orders are up 25 to 30 percent for the quarter ended Nov. 30.

Amelio has presided over a turnaround that has seen National's gross margin improve to more than 42 percent from 34 percent when it began its planned restructuring two years ago.

Key to the transition has been a move away from bipolar technologies--by closing or selling older fabs--and continuing a focus on analog and mixed-signal product development.

Orders in National's core analog and mixed-signal products area rose 30 to 35 percent in the last quarter.

Compaq sees growth in consumer niche

Burlingame, Calif. -- Compaq Computer Corp. could derive as much as half of its revenue from consumer products by decade's end, chief executive Eckhard Pfeiffer said last week.

Speaking at a personal-computer conference here, Pfeiffer said the rate at which the growth occurs, however, depends largely on how consumer markets evolve in certain regions.

"We're still in a commercial market that's growing very well," Pfeiffer said. "It's going to be hard for the consumer side to grow as quickly."

Currently, Compaq derives one-fifth of its revenue from consumer products.

Compaq has encountered problems in some of its forays into consumer areas. Last year, it was poised to jump into the personal digital assistant (PDA) business with a product of its own, but pulled back when the PDA market failed to ramp.

According to Dataquest , in the third quarter of 1994, Apple Computer edged past Compaq with the highest quarterly PC sales in the United States. It marked the first time this year that a PC maker other than Compaq has topped Dataquest's U.S. quarterly-shipments list. Compaq still leads for the year, however, with shipments of 1.7 million for the first three quarters of 1994.

Intergraph wins Seiko order

Huntsville, Ala. -- In a major win for its VeriBest design system, Intergraph Electronics announced that Seiko Instruments (Tokyo) placed an order that will guarantee sales of more than 1,000 seats of the Verilog-based VeriBest simulator by the end of 1995. Seiko is the distributor for Int ergraph in Japan.

According to Jeff Edson, vice president of Intergraph Electronics, the order means that a large share of the Japanese market will be using VeriBest. The potential for future orders could reach $10 million, he said.

The order includes Windows 3.1, Windows NT and Unix-based versions of VeriBest. Edson said that a significant number of Windows NT seats are included, demonstrating the growth of that platform in the Japanese EDA market.

Compaq eyes fix for Pentium glitch

By Brian Fuller

Burlingame, Calif. -- Compaq Computer Inc. is working to fix problems with its Pentium-based systems after recent disclosures by Intel Corp. that its Pentium CPU's floating-point unit is buggy.

Chief executive Eckhard Pfeiffer told an investment conference here last week that Compaq engineers are working to disable th e floating-point in existing systems.

"It gives customers the assurance that there's no problem in mode of operation," he said.

Pfeiffer did acknowledge that the fix does degrade the CPU's performance, but he declined to specify by how much.

At IBM, engineers are studying exactly how profound the problem may be, but still consider Intel's problem their problem, said G. Richard Thoman, a senior vice president at IBM.

"For most people using Pentiums in ordinary situations, this is no issue," he told the Technologic Partners PC Outlook conference. "But in intensive floating-point calculations, it's a problem with no boundary to it."

Thoman said that as of Dec. 3, 69 customers had called IBM hotlines set up to handle Pentium-related calls. Just two seemed to have a problem, he added.

IBM engineers are trying to understand the problem to determine whether a workaround might be needed, he said, adding that the floating-point unit is an option.

Intel acknowled ged last month that its Pentium floating-point unit occasionally makes incorrect divides, which can hurt high-precision calculations.

MRS meeting reveals future of electronics to be broad and deep

By Chappell Brown

Boston -- Commandeering three downtown hotels linked by upscale malls, the Materials Research Society gave Boston's Christmas shoppers the opportunity to rub elbows with 5,000 condensed matter mavens. Though their job descriptions might be impossible to decode, the materials scientists and engineers revealed extraordinary and potentially useful new processes and substances, as well as new approaches to the atomic level control of epitaxial film growth that should have immediate and far-reaching effects on electronics.

Electronics specialists would be hard-pressed to recognize their own field in the interdisciplinary diversity at the forefront of today's materials rese arch. What would a battery specialist make of a new "gellionic" material that feels like plastic, has elastic properties reminiscent of silly putty, and chemically operates like a liquid-lithium electrolyte? Prototype cells made from the new material, according to developer Bellcore Corp., either meet or exceed conventional lithium cells while reaping the low-cost advantages of solid-state polymers on the manufacturing line.

Also, optical-sensor specialists will have to bone up on their molecular biology to understand the operation of a new analytic sensor that combines optical-waveguide operation with antigen chemistry. Experts in biotechnology, electrochemistry, optoelectronics and micromachine technology are currently taking this basic antigen/optical effect to the commercial stage in a bid to empty test labs of bulky analytical instruments.

Researchers at Tel-Aviv University have developed a detailed model of bacterial self-organization at several levels that employs chemical-feedback path s combined with genetic learning. The model suggests an entirely new approach to the design of genetic algorithms and is part of a new field called genome cybernetics. One important application area will be new approaches to inorganic processes, such as semiconductor crystal growth.

Advanced AI concepts, such as machine learning, are being profitably applied to predict new materials. One system, described by N.N. Kiselyova, a scientist from the Russian Academy of Sciences, is trained on known results, and then turned loose on an open-ended set of problems. After compiling a computer-generated list of recipes for predicted compounds along with their physical, chemical and electrical properties, Kiselyova followed the directions in real laboratory runs. The results of the experiment showed that the computer had accurately predicted 80 percent of the compounds.

One of the major concerns of the conference was epitaxial film growth. Better control of the formation of crystal lattices at the surface of a growing film can be applied to etching and mask deposition, possibly leading to extending the resolution of current optical lithography. This new knowledge will also be indispensable in taking circuit definition below 0.1-micron dimensions, the next phase in the electronics revolution.

ISA moves into 3-D MCMs

By Terry Costlow

Woburn, Mass. -- Integrated System Assemblies has altered its chips-first multichip-module (MCM) technology, devising a way to stack several layers in a three-dimensional package.

Working under a three-year project funded by the Advanced Research Projects Agency and the Central Intelligence Agency, ISA developed a 1-Gbit solid-state recorder in a module that is only 3.2 mm thick. A key benefit of the technology, detailed at the International Society of Hybrid Engineers (ISHM) conference here last month, is that it works with different types of ICs. Th e recorder has multiple memories and controllers.

"Our package provides a 3X to 10X improvement in density," said ISA chief executive officer Don Jennings. "Most 3-D modules are just for memories, but ours can include CPU chips, memories and other chips. We can interconnect very high-pin-count chips, not just memories."

The ability to put entire systems or subsystems in a single compact package could have broad ramifications if the technology moves into volume production. The Gbit recorder holds 264 chips but measures only 33 x 63 x 3.2 mm. The eight-layer MCM is small enough to fit into a Type I PCMCIA card.

Designers can come up with systems that are very fast, since chips are close together. Heat dissipation is good because the chips are close to the substrate.

Destiny compresses printer images

By Ron Wilson

Santa Clara, Calif. -- Helping printer designers cut corners, Destiny Technology has provided a family of rendering, edge-enhancement and control ASICs that offload the most compute-intensive tasks in the printer, such as line and polygon-rendering or edge-enhancement. In the case of moderate-performance printers, these chips can eliminate the local CPU altogether, relying entirely on the personal-computer CPU to perform the computational work. This has produced a whole generation of processor-free low-cost printers.

A lot of computation is necessary to turn PostScript into a rasterized image. And that image takes up a lot of memory, especially with grayscale and color printers. So, it's hard to scrimp on either the printer CPU or the raster memory.

Destiny's D5001 band-rendering processor provides hardware engines both for rendering and for a unique memory-saving compression scheme. The former permits high-resolution printers to get by with a lower-cost CPU. The latter feature can drastically reduce the amount of buffer memory the printer need s to have, often with little impact on performance.

The basic concept is that if you can render fast enough, you don't have to do the whole page at once. Instead, you can render just a horizontal band maybe a couple of inches wide. If you can keep one band ahead of the print engine, everything will work smoothly.

But the way PostScript is structured, you have to traverse the entire command script for the page when you are doing each band. There is no way to divide the script up into commands that draw into the first two inches, versus commands that only draw into the second two inches, for instance. And if you try to work ahead, you still need lots of memory.

Destiny addresses the first problem by making the rendering hardware very fast. The second problem is also tackled by a hardware/software combination. Destiny has developed a unique adaptive-compression algorithm that keeps track of the remaining space in the band buffer. If space is getting short, the software will divide a previ ous band into blocks, and compresses the blocks.

The software has quite a battery of compression algorithms available, and chooses on a block-by-block basis based on the contents of the block. At least some of the algorithms are accelerated by the 5001 hardware.

Viewlogic updates PRO Series

By Richard Goering

Marlboro, Mass. -- In a significant upgrade to its Windows 3.1-based PRO series tools, Viewlogic Systems Inc. has revamped the user interface, added a work-flow management capability, and upped analog and digital simulation performance. The Version 6 release also improves VHDL synthesis for FPGAs.

Aimed mainly at PLD, FPGA and board-level design, the low-cost PRO series includes schematic entry, logic synthesis, analog simulation, VHDL digital simulation and interfaces to pc-board CAD. While earlier versions "substantially" conformed to the Windows user interface, th e new user interface uses the latest Microsoft widgets and is more intuitive, according to Scott McGrath, PRO Series manager at Viewlogic.

Version 6 also adds multiple-window support for simultaneous display of different schematic views, as well as enhanced palette and tool-bar support.

New to Version 6 is Viewlogic's "Intelliflow" technology, a work-flow management approach that guides the user through the sequence of tools needed to accomplish a design. The first implementation of Intelliflow is PROpld, which provides a process flow for PLD and CPLD designers. A similar offering for FPGA designers is planned for early 1995.

One significant addition to Version 6 is a new 32-bit simulation engine. PROsim/VHDL claims to run up to two and a half times faster than the previous PRO series simulator. However, it doesn't support the full IEEE 1076 VHDL specification, as do the Vantage simulators also offered by Viewlogic.

Intel's Pentium parry: revised CPUs begin to appear

By Alexander Wolfe

Santa Clara, Calif. -- Underscoring the open secret of chip design--there's no such thing as a flaw-free microprocessor--Intel Corp. said it has begun sending to selected users the first samples of its revised Pentium, which contains a fix for a bug in the chip's floating-point unit.

Meanwhile, the Internet flame war sparked by the bug took an unusual twist. Intel president and chief executive officer Andrew Grove posted a personal message apologizing for the floating-point "issue," which caused inaccurate results for some calculations.

Numerous net responses took Intel to task, more for its refusal to replace the bad chips on a no-questions-asked basis than for the existence of the problem itself. But Grove reiterated the company's policy of offering upgraded chips only to us ers engaged in heavy-duty scientific work.

An Intel spokesman said that about 50 customers have qualified so far to receive replacements. The first updated chips were sent last week to some of those users, he added. But volume shipments aren't scheduled until early next year.

At press time, the only user confirmed by EE Times to have received the new Pentium was Thomas Nicely, the Lynchburg College (Lynchburg, Va.) mathematics professor who kicked off the Pentium furor when he posted the first public notice of the flaw. Nicely, who received two chips from Intel prior to last week's shipment, said: "I ran my tests through over a quadrillion iterations with no errors, so I think it's safe to say it's free of the bug."

Jedec set to approve very-high-speed I/O spec: HSTL

By Ron Wilson

Washington -- It appears that the arguments about Gunning transceiver logic (GTL), center-tap ter mination and competing I/O standards are finally going to be settled. The logjam buster is a very high-speed I/O specification that has been approved by the Low-Voltage Committee of the Joint Electronic Device Engineering Council (Jedec) and passed on to the Jedec council, which is expected to grant final approval.

Known as high-speed transceiver logic (HSTL), the spec refines the original center-tap terminated (CTT) concept to produce a fast, flexible I/O scheme for integrated circuits. Even though semiconductor vendors aren't ready to call HSTL a final answer, many are pressing ahead with HSTL designs in their advanced memory chips. And one--Samsung Semiconductor--is already shipping HSTL device samples.

HSTL is actually a suite of interface specifications, all based on the same silicon structures but using different voltages and terminated in different ways. It addresses the need for very fast, low-voltage communications between chips on a board.

One of the specification types is desi gned for very fast point-to-point links, such as those between CPUs and cache SRAMs or between graphics controllers and frame buffers. Other types in the spec address more populous memory systems, including synchronous-DRAM main memory and memory systems populated with single in-line memory modules (SIMMs).

HSTL and TTL's other would-be successors

By Ron Wilson

Washington -- High-speed transceiver logic (HSTL) is only one in a long string of would-be successors to the seemingly immortal TTL I/O specification. In fact, TTL itself has fragmented into a variety of different structures in its attempts to cope with rising frequencies.

The basic problem is noise. In switching a signal between 300 mV and 4.7 V (or between almost 0 V and almost 5 V, in the case of CMOS) you necessarily generate a lot of harmonics. With the low slew rates of older technologies, that wasn't much of a proble m. But 0.5-micron CMOS can achieve very high slew rates, and pump a lot of energy into frequencies where transmission line effects spread them all over space and time. The result can be false clocking, interference on signal lines and other fatal problems.

The industry's first concerted response to the problem was almost incidental. When vendors moved to 0.5-micron processes, they had to reduce supply voltages to 3.3 V to avoid damaging the tiny transistors. In doing so, they also had to reduce the output swing of the chips to 0 to 3.3 V. That created what is known as low-voltage TTL (LVTTL), but more accurately should be called LVCMOS: low-voltage CMOS I/O. The threshold voltage at which a 0 becomes a 1 is the same as in good old TTL.

Initially, LVTTL looked like an interim solution, useful to maybe 75 MHz. But continued refinement of design techniques has extended its range to 150 MHz and beyond--if the design is done very, very well. Subtle changes in the silicon structures, including slew- rate controls, series resistors and built-in terminations have extended the life of LVTTL further, albeit at the expense of absolute compatibility.

The day of reckoning was anticipated several years ago, when a number of engineers, notably including Gunning at Xerox PARC, began developing a whole new type of CMOS I/O, more closely related to ECL than to TTL. The new schemes provided not only a signal line, but also a reference voltage--thus, the signaling was inherently differential. Instead of trying to compare an input voltage to ground, which might be bouncing all over the place, the inputs in these new schemes just looked at the difference between the input voltage and the reference.

That made it possible to get accurate data out of very low signal swings: hundreds of millivolts instead of several volts. Small signal swings, in turn, substantially reduced the amount of noise generated by the output stage.

The problem was that once the flood gates of innovation were opened, it wasn' t possible to admit just one idea. Gunning's transceiver logic (GTL), quickly accepted by a number of vendors, was soon attacked for having adverse characteristics when heavily loaded. New designs, using more elaborate termination schemes, emerged. These have included CTT, Fujitsu's terminated LVTTL, HSTL and Hitachi's ST Bus.

The good news is that most of the schemes use similar, if not identical, physical structures for inputs and outputs. Many vendors now feel that if they carefully control some additional process parameters, they can manufacture one output cell that will meet the requirements of most of the new proposals.

The bad news is that all of the schemes use slightly different voltages, terminations and so forth. And each one seems to be superior to any of its competitors in a few specific applications. So the industry might compromise on one Jedec-backed scheme like HSTL. Or it might continue to use a half dozen schemes, relying on silicon vendors to produce "universal" input and o utput cells that can handle almost any configuration.

The coming convergence crawl

By Junko Yoshida

Anaheim, Calif. -- It appears that 1995 will not see the commercial deployment of two-way broadband cable services. Instead, with the stampede to provide interactive TV to every home slowing to a crawl, there will be another round of trials.

The new timetable laid out by cable industry honchos gathered in Anaheim last week at the Western Cable Show calls for basic digital-cable set-top boxes in 1996. And, they added, a fully interactive box might not be ready until 2000.

For semiconductor companies, these delays could mean pressure to offer increased functionality at greatly decreased costs.

"There are a lot of technologies that are great to put in press releases, but they are not perfected today and are certainly not delivered yet," said John Malone, president and chi ef executive officer at Tele-Communications Inc. (TCI). "The closer we get to deployment, the less sure we become."

On the financial side, industry analysts are modifying their projected figures. Bruce Ryon, principal analyst on multimedia at Dataquest, a market research firm based in San Jose, Calif., said, "We are taking down the projected revenue of video servers on the interactive-TV market and pushing it back by a couple of years." As for market demand for compression chips such as MPEG, Greg Sheppard, director and principal analyst for semiconductor applications at Dataquest, noted that it is "unclear how the market bleeds after pent-up digital-satellite-terminal demand is met over the next six or eight months."

Pipelined SRAM becomes a Pentium bottleneck

By Ron Wilson

San Mateo, Calif. -- The fast-SRAM logjam that is retarding growth of the Pentium market could be broken up by a change of strategy by Intel Corp. on the design of secondary caches for the P54C processor. The move also could finally unleash the full performance of 66- and 75-MHz Pentium motherboards. But for most of 1995, the change of direction signals turbulence for fast-SRAM suppliers and motherboard vendors.

At issue is the type of SRAMs Intel recommends for Pentium secondary cache. Before the original P5 announcement, Intel had solicited a proprietary, 9-ns synchronous-burst-mode SRAM from a number of memory vendors, specifically to work with the Pentium chip. But the 9-ns parts proved hard to build and expensive, forcing motherboard designers to choose between expensive designs with capacity limitations or low-performance caches.

Apparently realizing how this could restrain the market, Intel reconsidered. The company suggested adding an output register to the SRAM design, making it a registered synchronous-burst SRAM, more commonly called a pipelined-burst S RAM. The additional register relaxed many of the timing constraints on the chip and made it theoretically possible for many more suppliers to build the part at reasonable prices. "Intel is now pushing the 32k-by-32 synchronous pipelined chip for operating frequencies above 66 MHz," said Michael Gulett, president and CEO of Paradigm Technologies Inc.

How pipelining saves the day

By Ron Wilson

San Mateo, Calif. -- The concept behind the pipelined synchronous burst SRAM is elegantly simple. It starts with the previously defined Pentium burst SRAM and adds an output register. That one addition magically releases timing constraints all over the chip.

The original 9-ns synchronous burst SRAM was also designed specifically for the Pentium cache application. The chip is designed to take in an address on the rising edge of the Pentium bus clock. The address and certain control information were latched on the clock edge. The latch drove the address decoders, which drove the memory array, and 9 ns later, data appeared at the output--just before the next address was latched in. The chip contains an internal burst counter, so it can provide four consecutive words of data in response to one address cycle in the interleaved sequence required by the Pentium primary cache. The timing was designed to be 2-1-1-1: two clocks for the address cycle, followed by three more data words on the next three cycles.

The problem with that design, according to SRAM vendors, was that it proved hard to build. When designers started studying the Intel spec, it turned out that the maximum access time from the clock edge was actually 8.5 ns at 66 MHz. That meant the latch had to be traversed, the memory array addressed, sense amps activated and at least 18 output drivers turned on, all in 8.5 ns. Most vendors found BiCMOS the only practical solution.

In contrast, the pipelined SRAM adds an output latch an d an additional cycle. The chip latches in an address and then spends a clock period performing the array access, just like the flow-through chip. But the data doesn't have to get all the way to the output pins--on the next rising clock, it is latched into the output latch, not actually appearing at the pins until sometime in the next cycle. Thus array access timing is relaxed, and the specs on the output buffers are relaxed, too. In exchange, the timing is 3-1-1-1.

Wireless world eyes Europe's GSM spec

By Junko Yoshida and George Leopold

Washington -- When the government opens its license auction On December 5 for broadband personal communications services, a variant of Europe's digital-wireless standard could lead the queue of contenders for early PCS implementations.

Analysts and some industry officials think wireless companies poised to enter the nascent PCS market will go with the proven Global System for Mobile Communication (GSM) variant known as DCS-1900 rather than wait for other multiple-access technologies, which are not expected to flower as standards until the end of the decade.

"Out of the chute, [the GSM variant] will be what these guys start selecting," predicted John Ledahl, principal analyst for personal-communications programs at Dataquest Inc. (San Jose, Calif.). "Those who can afford to wait will choose CDMA," or code-division multiple-access technology. Ledahl predicted CDMA will be the dominant U.S. standard by the end of the decade.

NTT pledges fiber to home by end of decade

By Loring Wirbel

San Francisco -- Japan's Nippon Telephone and Telegraph Corp. will have a fiber-to-the-home network throughout Japan by 2000. NTT will use a common Backbone High-spee_Cý ---onwide Network for Asynchronous Transfer Mode LAN/WAN services and cable TV distribution, said by Junichiro Miyazu, NTT's executive vice president, in his keynote speech at IEEE Globecom.

The common thread in presentations from Japan and Europe at last week's opening sessions was the promotion of a common physical infrastructure and protocol stack that will allow the rapid deployment of a Global Information Infrastructure (GII). With a common physical-layer base of Synchronous Digital Hierarchy/Synchronous Optical Network fiber to work from, researchers are as upbeat on the prospects of a GII as U.S. telephone companies are on the prospects of the U.S. NII equivalent.

Miyazu argued that NTT has a certain advantage in building infrastructure in Japan, thanks to the low rate of penetration of cable TV services in Japan. The 1.63 million subscribers for broadband cable in Japan (there are 55.7 million in the United States) represent only a 4.7-percent market penetration of potential homes. Consequently, he said, NTT does not need to worry about an installed base of c oaxial cable in Japanese homes and does not need to consider hybrid fiber/coax alternatives to pure fiber-to-the-home.

In a luncheon keynote, IEEE Communications Society president Maurizio DeCina provided views of Europe's transition to broadband networks, though he emphasized that Europe and North America will have to rely on a variety of hybrid architectures to merge new fiber distribution vehicles with existing twisted-pair and coax worlds. DeCina focused on an issue that he said will become more important over time: the choice of transport protocols for carrying multimedia information.

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