EET-i Top of the News

Week of Nov. 28, 1994

Thursday, Dec. 1, 1994

National acquires stake in Synaptics
Orbit Semiconductor issues IPO
Electric-car firm wins federal deal
Report: handheld organizers to beat PDAs

Wednesday, Nov. 30, 1994

Siemens, SGS link on microcontrollers
Britain boards the information highway
CAD/CAM market set for a rise
Swedes select Digital video server
Italian startup buys TI assembly plant

Tuesday, Nov. 29, 1994

Oxford's CAM-cell FPGA will support more circuit styles
MPEG plugs into PCs
PCI bus exerciser slashes development time
NTT synthesis comes to U.S.
Dc/dc converter powers mobile systems

Monday, Nov. 28, 1994

Optobus plugs cluster-linking gap between Firewire and Fiber Channel
Siemens to restructure IC operation
Analog VHDL confronts controversies
Coldfire: The long road to a new architecture

National acquires stake in Synaptics

Santa Clara, Calif. -- National Semiconductor Corp. last week took a stake in Synaptics Inc. as part of an alliance in which the pair will develop sensory-based technologies.

Under the agreement, Synaptics, which specializes in computer interfaces, will give National access to its hardware and software technology. National will manufacture products that emerge from the deal and will help develop worldwide markets. The amount of National's investment in Synaptics, founded in 1986 by Federico Faggin and Carver Mead, was not disclosed, but National will get a seat on Synaptics's board.

The companies hope to develop products that will improve computer-control technologies and play off senses such as sound, sight and touch, the companies said in making the announcement.

Orbit Semiconductor issues IPO

Sunnyvale, Calif. -- Orb it Semiconductor Inc., an ASIC and manufacturing-services company, has begun trading its stock publicly on the Nasdaq national market.

The company said the trading of 2.3 million shares of common stock began Nov. 16 under the trading symbol "ORRA." The initial public offering price for is $7.50 per share of common stock.

Electric-car firm wins federal deal

Santa Rosa, Calif. -- U.S. Electricar Inc. has won a $10.5-million, five-year contract from the Commerce Department to develop cost-effective manufacturing of lightweight and affordable electric vehicles.

U.S. Electricar said it will be the lead company in developing a process to make recyclable, lightweight components that would be cost-effective for expected electric-vehicle production runs in the 1,000- to 25,000-per-year range.

Under terms of the Commerce Department's National Institute of Standards and Technology's Advanced Technology Program, the program will provide $21.8 million in matching funds, with $10.5 million in direct support to the company, U.S. Electricar said.

U.S. Electricar officials said they believe the program should help it introduce the next generation of electric vehicles.

Report: handheld organizers to beat PDAs

New York -- In the "smart" handheld-device market, organizers will sell better than PDAs or personal communicators in the near term, a new report by research firm Link Resources contends.

The reason: Better-than-anticipated shipments in organizers from Sharp Electronics Corp. and Hewlett-Packard Co. Link said it reduced its 1994 and 1995 forecasts for PDAs and personal communicators because of delays in the shipment or introduction of products from companies such as IBM, Motorola and Sony; the disappointing sales of Newtons; and the closing of AT&T's EO subsidiary earlier this year.

While downgrading the forecast on two product areas, Link expects smart handheld device shipments in the United States to reach 784,000 units in 1994 and grow in the coming years at 49 percent annually.

Siemens, SGS link on microcontrollers

Munich, Germany -- Siemens and SGS-Thomson Microelectronics (STM) have extended their cooperation on 16-bit microcontrollers with the introduction of a third device to be second-sourced by both companies.

The SAB-C165 from Siemens and the ST10R165 from STM offer the same 100-ns instruction-cycle time as previous devices but has a reduced set of peripherals to help it target cost-sensitive embedded applications. Applications targeted by the device include hard-disk drives, modems and communication controllers.

A version of the original device, th e ST10F166 and SAB 88C166 from STM and Siemens respectively, includes 32 kbytes of flash memory. STM has developed flash versions of the 16-bit microcontrollers, which are available from both companies, even though STM has not transferred the flash technology to Siemens. Instead, STM manufactures flash versions on behalf of both companies while Siemens makes ROM versions for both companies.

Britain boards the information highway

London -- The British government is moving onto the Infobahn in a big way. Ian Taylor, Trade and Technology minister at the Department of Trade and Industry (DTI), has been named to coordinate the DTI's interests in broadband communications and multimedia for the information age.

Taylor's responsibility for encouraging development of the Infobahn was announced the same day that the DTI published its report: "Creating the Superhighways of the Future: Dev eloping Broadband Communications in the U.K." This sets out the government's position on telecommunications policy and the regulatory framework for national telecom-service providers and local cable-service providers.

One of the conclusions of the report is that the government should make more use of the information highway itself, which prompted the posting of the report on the World Wide Web.

CAD/CAM market set for a rise

Cambridge, Mass. -- Worldwide CAD/CAM, CAE software revenues will top $4.1 billion this year, a growth of 8.5 percent over 1993, according to a new forecast from market researcher Daratech Inc.

Much of this year's growth will come from the current roster of top-tier companies. The report also notes that improving economic conditions in North America and Asia, together with continuing recovery in Germany and the United Kingdom, also helped to stimulate CAD/CAM, CAE software revenue growth in 1994.

Swedes select Digital video server

Stockholm, Sweden -- Digital Equipment Corp. has garnered a Scandinavian video-server sale. In what the company claims is one of Europe's first video-on-demand trials conducted by a cable company, Svenska Kabel-TV and Telia AB--the Swedish national telephone service provider--will test a video-on-demand service in 500 suburban Stockholm households beginning early next year.

Digital will provide its head-end video server and Middleware software. Vela Research Inc. will provide the MPEG-2 decoder cards that convert server signals into analog to travel over the cable operator's existing network.

Italian startup buys TI assembly plant

Rieti, Italy -- EEMS Spa, a startup, announced it will acquire Texas Instrument Inc.'s MOS memory assembly and test operations based here.

EEMS has bought the shares of the operation, Manufacturing Services International Spa, and will keep the 680-person workforce and use some existing management to run the facility. The operation will remain here and will continue to provide manufacturing services for TI.

EEMS also will expand its assembly and test subcontracting services to customers worldwide.

Officials claim the Rieti operation becomes the first worldwide subcontracting service dedicated to DRAMs and will expand test capability to handle 4-Mbit and 16-Mbit parts.

EEMS was recently formed by T.L. Li, a Hong Kong investor who has interests in IC assembly and test, lead-frame manufacturing and silicon wafer manufacturing.

In a related move, EEMS announced it has licensed IBM's lead-on-chip technology used in the packaging of DRAMs.

Oxford's CAM-cell FPGA will support more circuit styles

By Peter Clarke

Oxford, England -- There is a better way to build FPGAs than the Xilinx approach of SRAM-based lookup tables to define configurable-logic blocks. So says Dr. Ian Page at Oxford University's Computing Laboratory. He argues that an array of content addressable memory (CAM) cells will better support a wider range of circuit types, including memory arrays. He has patented the idea, and is looking to license the technology to one of the major FPGA makers.

Page has found interest elsewhere. "There's nothing approaching being signed and sealed, but we've got close to one of the companies which is a leader in FPGA. They seem quite interested," he said. Page declined to name the company but did rule out Xilinx.

Hardware compilation research around the world's universi ties typically uses pc boards loaded with FPGAs, usually Xilinx devices, to implement its ideas.

"We noticed that none of the available devices has the full set of attributes to support automatically designed systems. We drew up a wish-list and our FPGA represents that," Page said.

One of the ideas behind hardware compilation is that the hardware to support a program can be configured or optimized by the program itself. As a by-product of the labs' work, Page has developed strong ideas about FPGAs and has patented an approach based on content addressable memories as the fundamental building block for field-programmable logic.

According to Page, the use of CAM allows the implementation of all the circuit types supported by RAM-based designs, as well as arbitrary-sized programmable logic array (PLA)-type circuits. He said that PLAs, based on a plane of AND gates feeding into a plane of OR gates, have an advantage over the SRAM lookup-table approach for circuits requiring a large nu mber of inputs and/or outputs. A typical example is the wide address decoder, which is not efficiently implemented in an FPGA based on lookup tables.

In Page's design, the most basic cell is 1-bit CAM. He proposes these be arranged in a 4 x 4 array with four bidirectional interconnections from each 1-bit cell to form the equivalent of the Xilinx CLB. Page pointed out that this could be used as a 16-bit lookup table but, because it has four outputs as well as four inputs, it can be used to contain one function of four variables, two functions of three variables or four functions of two variables. Besides four inputs and four outputs, the 4 x 4 cell provides four signal lines in each direction (N, W, S, E) for local connections between nearest-neighbor cells, without calling on an implementation's global routing network.

In addition to implementing the CLB, the CAM array can be used to form arbitrarily large PLA structures and, not surprisingly, can form arbitrarily sized CAMs, or more conve ntional SRAMs. The final advantage Page claims for his architecture is that its fine-grained nature makes it more accommodating for software to place logic macrocells onto.

MPEG plugs into PCs

By Rick Boyd-Merritt

Fremont, Calif. -- MPEG decompression playback-adapter cards made a big showing at the recent Comdex/Fall. Leading the new board-level announcements was a card from Sigma Designs Inc.

Sigma is one of the first companies to offer an MPEG video-playback card for the PC. RealMagic Rave is a version of the company's MPEG decompression board married with a VESA local-bus graphics accelerator.

Following in the footsteps of the market leader, Orchid Technology, also based here, released an MPEG/GUI accelerator board for the VL-bus. Orchid adopted the same EM7000 MPEG chips used by Sigma in an effort to leverage the growing pool of developers writing titles for the Sig ma MPEG cards and Sigma-defined API. Orchid uses the 64-bit CL-GD5434 graphics accelerator from Cirrus Logic.

Vendors suggest the new MPEG boards are the next wave in PC multimedia, to be followed by a mix of hardware and software MPEG boards in 1995. Those boards will be followed by all-in-one multimedia adapters, appearing perhaps by midyear.

Many independent hardware vendors see a trend in next-generation boards toward adapters that mix and match hardware and software compression. "This time next year, hybrid hardware/software MPEG boards will be everywhere," said Peter Cattaneo, a vice president at board maker Genoa Systems Corp. (San Jose, Calif.).

Ultimately, the multimedia card makers are exploring the move to single-card multimedia solutions, aimed at accelerating graphics, MPEG and audio with new "media chips" coming from chip makers such as Brooktree, Nvidia and others. "We are looking at a generic device that speeds up all the multimedia processes," said Adam Silver, a prod uct manager for graphics and digital video at Orchid. "It would help decode MPEG video and audio streams, handle wavetable sound synthesis and graphics acceleration."

PCI bus exerciser slashes development time

By Stan Runyon

Palo Alto, Calif. -- For engineers who wish to design the Peripheral Component Interconnect (PCI) bus into their products, Hewlett-Packard is offering some help: a PCI bus exerciser.

The bus exerciser works with the user's PC and an HP 16500B/16550A logic analyzer to help bring up, debug and validate PCI designs. Developed at HP's Boeblingen, Germany, division, the HP E2910A simulates devices deterministically--that is, with bus traffic that emulates the real-world conditions of the final application.

Designs, including ICs, system motherboards or plug-in cards, appear as emulated hardware or as prototype/final devices.

Included in the HP E29 10A are Windows-based software, a test sequencer PC plug-in card, a PCI bus exerciser card and a choice of adapters for in-system and card test.

According to HP, the exerciser, which operates at 33 MHz, can lop several weeks off development because users do not have to wait for actual PCI hardware. Time can be saved at all stages of product development: ASIC emulation, prototyping, writing drivers, integrating and validating.

Exhaustive verification is possible when the first device becomes available. For example, by deploying the HP unit as a known independent reference, users can exercise all variations and stressful corner cases within the PCI protocol. They can record, replay and modify real traffic to reproduce critical cases and quickly isolate basic causes of problems.

NTT synthesis comes to U.S.

By Richard Goering

Woburn, Mass. -- A high-level synthesis tool set developed by NTT Data Systems and used by several Japanese companies is making its U.S. debut with the release of Parthenon version 2.3. Targeted for shipment in the first quarter of 1995, the set will be sold by Harmonix Corp., a software development and marketing organization here.

Though Harmonix has exhibited Parthenon at the last two Design Automation Conferences, the latest release marks the first major attempt to penetrate the North American market, said Steve Adams, director of technical marketing at Harmonix. Version 2.3 adds a graphical user interface to a tool that was previously command line-driven.

Unlike other commercial synthesis products, which use VHDL or Verilog, Parthenon is based on NTT's proprietary SFL language. This C-like language, specifically designed for synthesis, permits users to describe electronic systems in terms of state machines. SFL extends C with support for concurrency, parallelism and pipelining.

NTT claims that Parthenon offers "behavioral" synt hesis, but the tool set does not conform to the definitions generally accepted in the industry. For example, it doesn't perform automatic scheduling or multicycle resource allocation. Scheduling is implied in the state-machine descriptions that are fed to the tool.

However, SFL still permits design entry at a very high level, according to Adams. "There's no information about connections," he noted. "In VHDL, you have to say that signal A will go to signal B. In our system, it's like programming--you just make a call to a function and pass in arguments."

The result, according to Adams, is a tool set that's easy to use. "If you're familiar with C programming, you can pick up this system and the syntax is understandable to you. I come from a software background, and I can now design chips."

Parthenon is especially well-suited for applications such as DSP and video, he added. The tool requires synchronous, single-phase designs, though there can be multiple clocks that are harmonics of the phase clock. The tool is in production use at Fujitsu, Mitsubishi, Nissan, Sanyo, Sharp and Toshiba, as well as NTT.

Dc/dc converter powers mobile systems

By Ron Wilson

San Jose, Calif. -- Dc/dc converters have been lost in the avalanche of publicity for low-voltage systems. In the rush to get 3.3-V memories, 2.5-V microcontrollers and even low-voltage power amplifiers to market, there hasn't been much discussion of where the voltage would come from.

The best of all possible worlds, of course, would be to drive the circuitry in a mobile device directly from the battery. But with popular battery technologies like NiCd or NiMH, unregulated connection to the battery means a huge range of operating voltages. A NiCd cell may start at a bit over 1.5 V when fully charged--enough to pop inputs on carelessly specified low-voltage chips--and droop to near 1 V as it approaches full discharg e. It is often possible to specify or design chips to meet their specifications over that entire range. But it isn't trivial, and with mixed-signal chips it may not be realistic. Further, you will give up much of the performance of the chips just allowing for the supply-voltage range.

A better approach for many designs is a single-chip dc/dc converter. Such a device would take in the battery voltage and provide an output voltage regulated to within a few percent. But such chips have tended to be inefficient converters. Much worse, they often draw static power, the cardinal sin for mobile electronics.

Micro Linear has announced an alternative. The ML4875 dc/dc converter family accepts input from a battery at as little as 1 V and produces a regulated output at 5.0 V, 3.3 V, 3.0 V or an adjustable voltage between 2.5 V and 5.5 V. You have to specify which version you want.

Regulation is plus or minus 3 percent, using a synchronous rectifier and pulse-frequency-modulation techniques. The c ompany claims the chip is 90 percent efficient. Additionally, the part will disconnect itself from the battery when the system is shut off or an external supply is connected, eliminating static drain on the precious cells.

Optobus plugs cluster-linking gap between Firewire and Fiber Channel

By Loring Wirbel

Phoenix -- There's a shortage of ultrahigh-speed parallel links ideal for tying together clusters of servers or mass-storage units. So Motorola Inc. will introduce next Tuesday a new parallel-link technology that will enable multichip modules to operate as high-throughput data subsystems. Called Optobus, the 10-channel bidirectional optical link appears to plug the gap between low-cost but moderate-performance desktop links like Firewire, and high-speed but high-cost serial standards like Fiber Channel. It was developed by Motorola's l ogic IC group here and its corporate R&D labs in Tempe, Ariz.

Optobus is based on multichip modules that contain integrated surface-emitting lasers and current-mode logic (CML) ICs. It uses two 10-channel ribbons per module, so that bidirectional parallel links are set up with 10 transmit and 10 receive links capable of operating simultaneously. Since each multimode fiber channel can handle 150 Mbits/second throughput, the modules have an aggregate throughput of 1.5 Gbits/s in both directions.

The technology will be positioned as a physical-layer data mechanism that fits between the Scalable Coherent Interface (SCI), an expandable copper twisted-pair parallel technology intended for in-system applications, and long-haul serial links such as Fiber Channel, said Jess Diaz, marketing manager for the program. Optobus can operate over distances of up to 30 meters for clustering applications, and may be extendable to 100 meters.

The real advantage that Motorola wants to push with O ptobus is the integration of opto-transceiver technology into the I/O circuit module, allowing network developers to create an optical connection simply by plugging the 10-channel ribbon into the transceiver multichip module.

Siemens to restructure IC operation

By Martin Gold

Munich, Germany -- Siemens AG, the German electronics giant, has restructured its $2 billion semiconductor operation to refocus on the global merchant market for telecommunications chips. In the process, said Semiconductor Group president Jurgen Knorr, the unit has shifted from a largely technology-driven operation to become more market-, applications- and customer-driven.

"We phased out many of our company's older, bipolar standard logic and 16-bit microprocessors and two of our old manufacturing facilities in Munich," Knorr disclosed in an interview here shortly after the close of the Electronica trade fai r. The merchant market accounted for 80 percent of the operation's revenue in its most recent fiscal year.

Siemens also seeks a broader, more global scope for the semiconductor operation. In the past, Knorr said, the group has "paid too much attention to our European regional market."

Among the thrusts will be chips and chip sets for digital cellular communications -- a market in which Siemens competes against nearly a dozen other vendors, including Texas Instruments Inc., Motorola Inc., Philips, GEC Plessey, AT&T Microelectronics and Analog Devices Inc. Unlike some of its competitors, however, Siemens has a broad portfolio of dedicated ICs, RF/power discretes and optoelectronic semiconductors for the telecom market.

In addition, Siemens, which already has successful alliances with IBM Microelectronics and Toshiba Corp. in memory technology development, is scouting further alliance partners, especially in the United States.

Analog VHDL confronts controversies

By Richard Goering

Santa Clara, Calif. -- The IEEE is trying to develop a standard analog hardware-description language based on VHDL, but the effort is bogged down in controversy in the EDA community over whether two vendors have jumped the gun with products based on the standard's early version.

The idea behind analog VHDL is to take the existing VHDL digital language and add extensions for time-domain analog simulation. It was set up last year as an IEEE project with a timetable calling for language design and documentation to be completed next June. But the job is taking longer than expected and is running into fundamental industry differences over how early is too early.

The problem is that Anacad and Cadence have already come out with products that the companies said support a preliminary version of the IEEE 1076.1 standard. At a news briefing here last week sponsored by Analogy Inc. (Be averton, Ore.), participants criticized Anacad and Cadence for releasing those products. But Analogy has a proprietary analog HDL product called Mast that it plans to continue supporting even as it supports the eventual IEEE standard, via a new separate product.

Representatives of Anacad (Ulm, Germany), which is now a Mentor Graphics subsidiary, and Cadence Design Automation (San Jose, Calif.) said last week they are not claiming 1076.1 compliance and that they intend to support whatever final standard emerges.

Meanwhile, there's no indication that this controversy is undermining technical work on the standard, even if that work is already late.

Coldfire: The long road to a new architecture

By Ron Wilson

Austin, Texas -- Motorola had a gap in its product line right where emerging multimedia and communications markets were asking for ASIC CPU cores; missing was a core with about the die area of a 68000 but with performance ranging up to 40 Dhrystone Mips or more.

And that's why the company with the world's most successful 32-bit embedded-microprocessor family, the world's dominant 32-bit microcontroller family and a growing line of embedded PowerPC CPUs developed a new 32-bit architecture--and in the bargain abandoned instruction-set compatibility with all of the earlier families.

Enter Coldfire, the new architecture that tiptoed into the world with little ceremony at the recent Microprocessor Forum. Qualifying on both real estate and speed for the mini-RISC category, the chip will take its place in the arena that includes the ARM7, the Hitachi SH, the NEC V800 and the most recent MIPS embedded cores. But Coldfire, nested in Motorola's ASIC methodology, will have to interact with other advanced functional cells in Motorola's repertoire if it is to compete against formidable ASIC vendors.

So why didn't Motorola simply do a shrink version of one of the more powerful 68k CPUs, massage it into shape for an ASIC library and release it?

One reason was methodological. "Historically, we have always had to re-implement our CPU cores every time we changed processes," acknowledged Jim Reinhart, manager of embedded-systems engineering and marketing. "We have never had the cores in a form that would be easily portable from one process to another." Additionally, there were architectural problems with shoving any of the existing 68k CPUs into the breach.

A profitable share of the emerging communications, information and consumer markets is the prize. And time will tell.

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