EET-i Top of the News

Week of Nov. 21, 1994

Wednesday, Nov. 23, 1994

BT sets ADSL interactive-TV trial
SOI-wafer maker Soitec wins secondary funds
Worldwide memory market is on the rise
Nintendo preps virtual reality game machine
VHDL, Verilog gurus get the call at Analogy

Tuesday, Nov. 22, 1994

MEMS targets 3-D VLSI
Cadence Combines Two Tools In `Silicon Synthesis'
NSC rolls routing switches, including a 1.6-Gbit unit for ATM
Simtek debuts submicron 256k NVSRAM
New silicon-carbide process

Monday, Nov. 21, 1994

Intel's Grove calls for improved PC architecture
Samsung sets transition to 12-inch wafers
Europeans team for on-chip bus standard
Kodak researchers aim to take error correction mainstream
Open Set-top group plans modular architecture
Intel outlines Pentium warranty

BT sets ADSL interactive-TV trial

Ipswich, England -- BT is poised to begin consumer trials of its interactive-TV service, based on asymmetric digital subscriber loop (ADSL) technology. The trials will include 2,500 households and are scheduled to begin in mid-1995. BT is linking up with a wide variety of service providers: TV and satellite-TV companies, banks and Main Street shops, to run services over the system. BT is making the move even though the British government has confirmed its ban on BT's offering television entertainment and home-shopping services before 2001.

Following a previous technology trial, BT concluded that ADSL technology has a wider range--about 6 km--than expected, and the combination of MPEG compression and ADSL works well. The technology trial used Apple Macintosh 475 computers running Mac O/S as the set-top box. That was adapted to support MPEG and a 2-Mbit/second network. ADSL running over copper was used to deliver a 2-Mbit/s delivery channel and a 9.6-kbit/s bidirectional control channel plus an analog telephone service.

The market trial will be based in the Ipswich and Colchester areas and involve the same technology providers as for the technology trial. Oracle will provide the multimedia database and na vigational software; Ncube will provide the multimedia server; Sequent is to provide customer management software; and Apple will provide the set-top systems. For the market trial, BT will use optical fiber as well as ADSL over copper. A switching, concentration stage will also be added based on Asynchronous Transfer Mode technology.

SOI-wafer maker Soitec wins secondary funds

Grenoble, France -- Soitec, the silicon-on-insulator (SOI) wafer maker, completed a second round of venture-capital financing, the company announced last week. Company officials did not disclose the amount of capital raised, but they said it was to be used to expand the 28-person staff and increase manufacturing capacity.

"The silicon-on-insulator industry is extremely capital intensive, and planning adequate manufacturing capacity is essential to be successful," said Jean-Michel Lamure, Soitec's president. "That' s why we chose this time to increase our financial capabilities."

Soitec was spun from Laboratoire d'Etudes et de Technologique del l'Informatique (LETI), the French technology lab, in 1992 to pursue SOI technology on a commercial basis.

Worldwide memory market is on the rise

Mountain View, Calif. -- The worldwide market for memory chips is expected to grow from $26.9 billion this year to $59.1 billion in 2000, according to a new report from analyst Frost & Sullivan Inc. Despite the overall upward trend, the growth rate for the rest of the decade will fluctuate due to variations in demand from the computer and peripherals industries.

The report also noted that the development of more powerful microprocessors should increase the demand for faster SRAM and specialty chips. In addition, rising memory densities are expected to spark new applications, particularly for fl ash and EePROM devices.

Nintendo preps virtual reality game machine

Kyoto, Japan -- Nintendo Co. has unveiled VirtualBoy, a virtual-reality (VR) game machine with an eyeglass-like display that will be marketed in Japan and the United States beginning next April.

The system is based on NEC's 32-bit RISC CPU, the V810. Its display technology was developed by Nintendo and Reflection Technology Inc. (RTI; Waltham, Mass.), based on aerospace technology. Nintendo has been working with RTI for two years to combine RTI's head-mount display technology with Nintendo's 3-D-effect technology, said a Nintendo spokesman. Nintendo has an exclusive RTI license and may invest in RTI, the spokesman said.

VirtualBoy has two LED displays for the user's right and left eyes. Red images projected onto the black background create the 3-D images.

VirtualBoy will cost about $200 in Japan. The U.S. version will be announced at the Consumer Electronics Show in Las Vegas in January, the spokesman said. Nintendo said it expects to sell 3 million units in the first year, along with 14 million game cartridges. The portable unit operates for seven hours on six AA batteries.

VHDL, Verilog gurus get the call at Analogy

Beaverton, Ore. -- Foreshadowing a more aggressive move into hardware description languages (HDL), Analogy Inc. has hired Charles Swart, a well-known VHDL expert, and Steven Greenberg, a Verilog-simulation specialist. Both are joining Analogy's simulation technology team, which is charged with support for IEEE 1076.1, the emerging analog VHDL standard.

Swart was previously a senior software engineer at Mentor Graphics Corp. (Wilsonville, Ore.). He serves on several IEEE 1076 committees, and is a prominent VHDL technologist. Greenberg led mixed-signal simulator develop ment at Cadence Design Systems (San Jose, Calif.).

The company has a well-received analog simulator and plans to introduce a digital/analog simulator next year, once the proposed 1076.1 analogy VHDL standard(see Nov. 14, page 36)settles down.

MEMS targets 3-D VLSI

By Chappell Brown

Berkeley, Calif. -- Chafing under the two-dimensional limitations imposed by current VLSI processes, micromachine experts are pushing into a new technology area that promises full three-dimensional capability. New materials and etching methods, combined with electronic-design-style computer models, could create a more tightly integrated form of micro-electromechanical system (MEMS) that transcends the two-dimensional plane.

Designers have already taken the first tentative moves toward a third axis in circuit design with the complex layering o f metals and with such three-dimensional structures as trench capacitors--what is sometimes described as "2.5-dimensional" design. MEMS designers haven't felt obliged to work within the established constraints of planar silicon processing, however.

The University of California's Berkeley Sensor and Actuator Center, for example, is mounting a broad attack on the problem using established expertise in porous-silicon processes. Porous silicon etches away at a much faster rate than the denser, crystalline silicon--a characteristic that's being put to use in defining vertical trenches in silicon.

Much more can be done with the differential-etch-rate technique when knowledge from the field of electrochemistry is factored into the process. "This is a truly interdisciplinary effort. We have been fortunate in being able to tap some of the top talent in electrochemistry to establish new three-dimensional etching methods," said Richard Muller, a Berkeley electronics engineer who is working on a project t o exploit porous-polycrystalline silicon.

"The new process has allowed us to build stronger, more-complex three-dimensional cavities interconnected by complex fluidic channels," Muller said. "It could have great utility in medical and chemical technology."

A project at the California Institute of Technology (Pasadena) is attacking the problem at the simulation and design level and could produce the first true three-dimensional design system for silicon VLSI processes. The brainchild of Erik Antonsson, a specialist in engineering design, the new CAD system will allow a designer to specify the functions of a microelectromechanical part. The system will then generate a set of masks that can be handed over to a manufacturing line.

"A few years ago, it occurred to me that, in order to evolve, micromachine technology will need the same kind of design tools that have become common in electronic design," Antonsson said. "Currently, the process of building a micromachined part involves a seri es of steps that require a lot of intuition. First, you consider the kind of structure you want, then a shape that can be feasibly implemented in the materials system is designed, and that finally leads to a set of masks."

Cadence Combines Two Tools In `Silicon Synthesis'

By Richard Goering

San Jose, Calif. -- Introducing a new technology called "silicon synthesis," Cadence Design Systems Inc. is bringing full IC placement into the front end of the design cycle. Silicon synthesis will result in a product that combines Cadence's existing Placement Based Synthesis (PBS) optimizer with an enhanced version of QPlace, Cadence's fast quadratic placer.

While many vendors are working to link synthesis with layout, Cadence's approach is distinctive because it will enable logic designers to produce a full placement as well as a net-list. The technology is aimed at eliminating iterations be tween synthesis and layout. "This is part of a cultural transition we will have to go through to do deep-submicron design," said Tom Katsioulas, marketing manager for advanced technologies at Cadence's HDL design group.

Katsioulas acknowledged that bringing placement to logic designers will be an evolutionary process. PBS and QPlace are primarily back-end tools today, and the new silicon-synthesis approach requires floor planning, which is also mostly done by layout designers. Cadence's existing Preview floor planner is a gate-level tool, but the company is working on a high-level floor planner aimed at logic designers, Katsioulas said.

Cadence is currently taking silicon synthesis into beta sites that do both logic and layout design. The intent, however, is to create what Katsioulas calls a "front-end-use model" in conjunction with the forthcoming high-level floor planner. Product introductions based on silicon synthesis are expected in the first half of 1995.

The basic silicon-synthe sis flow involves three major components. First, QPlace does an initial placement after synthesis and estimates interconnect delays. Next, PBS reoptimizes the logic to remove timing violations and minimize interconnect delays. Finally, QPlace incorporates these logic changes, producing a final net-list and placement that meets synthesis timing constraints.

Silicon synthesis is a standalone process, which can be used with synthesis tools from Synopsys as well as Cadence, Katsioulas said. For now, it needs to use Preview before the initial placement, to place chip I/Os and large macros. Once that's done, however, it's an automatic, batch process that requires no user intervention.

NSC rolls routing switches, including a 1.6-Gbit unit for ATM

By Loring Wirbel

Minneapolis -- Network Systems Corp. (NSC), the switching and routing specialist that recently merged with Storage Technology Corp., has introduced the first members of its Enterprise Routing Switch (ERS) family, a backbone frame and cell-switching architecture. ERS was one of the elements of NSC that attracted Storage Technology's interests.

The 1.6-Gbit non-blocking switch at the heart of ERS will be touted as an ideal central location for both routing and Asynchronous Transfer Mode (ATM) switching, particularly at the interface where LAN meets WAN. The hardware architecture is combined with a Networks-On-Demand software suite that allows full virtual-network creation, as well as sophisticated policy-based flow control to handle mixes of data and isochronous traffic.

The switch architecture has all intelligence resident on interface modules, with no centralized control processor. The Intel i960 is used for packet acceleration in both router and ATM environments and is combined with an ASIC developed at NSC called the Fast Packet Processor (FPP).

Thomas Gilbert, director of marketing for routers and switches at NSC, said that routing speeds in excess of 500,000 packets/second will be possible through the combined i960-FPP architecture. ATM cells can be processed at 3.25 million cells/s.

The switch has two 800-Mbit/s cell buses for packet traffic, as well as a separate control bus. LAN and WAN modules are hot-swappable, and can be configured for full redundancy in both LAN connections and in power-supply use. The Network-on-Demand software allows network managers to assign priorities through the NetSentry management package, so that highest-priority applications receive bandwidth requests first.

ATM modules will support ATM Adaptation Layers (AAL) 1 and 5 immediately, with additional AALs for isochronous traffic added later. Data can be carried over IP/ATM protocols, native ATM protocols or LAN Emulation methods.

Gilbert said that NSC "will also support a trunking protocol to carry continuous bit-rate traffic over existing digital lines like DS-1. That way, customers don't have to wait unt il their public carriers provide ATM services, which might be several years away in some cases."

Simtek debuts submicron 256k NVSRAM

By Loring Wirbel

Colorado Springs, Colo. -- Simtek Corp. has gotten first samples of a 256-kbit non-volatile SRAM from its foundry partner, Chartered Semiconductor, and will provide several product types to customers over the next few quarters. First to ship are 32k x 8 versions: the STK15C88 device, with the AutoStore storage-on-power-down feature; and the STK11C88, without AutoStore.

L.D. Hockaday, director of sales and marketing at Simtek, said other versions to come in 1995 include a surface-mount memory with extra sleep-mode features, the STK12C88, and a device with a 16k x 16 configuration. He said, "The 16-bit-wide parts will prove important in DSP applications. We are currently running wafers that have one 16-bit-wide memory for every six 8- bit parts, so we will be able to have tested, wide memories ready in the early part of next year."

Simtek was the originator of a silicon-nitride-process technology that allowed easier integration and process shrinks of non-volatile memory cells on standard CMOS lines than traditional thick-film EePROM technologies.

"We will bring up our 64k memories on Chartered's 0.8-micron process as well," he said. "Luckily, we only lost two customers during the uncertainties earlier this year. We have many design wins at 64k who are ready to upgrade to 256k products."

The Simtek memory design uses standard SRAM cells with shadow EePROM cells. The AutoStore firmware in the STK15C88 monitors the system power supply continuously, and initiates "Store" operations whenever voltage drops below a certain level. Data is then transferred to EePROM until power is restored. Users can store and restore data through software commands and can conduct unlimited recall cycles through EePROM. SRAM read accesses ar e also unlimited, and EePROM stores have a guaranteed minimum of 100,000 cycles.

New silicon-carbide process

By Chappell Brown

Livermore, Calif. -- The use of buckminsterfullerene, a novel form of carbon, with standard photolithography may provide a new route to integrating silicon-carbide structures into circuits and micromachined parts.

The new process, devised here at Lawrence Livermore National Laboratory, has allowed researchers to grow high-quality silicon-carbide films up to 1-micron thick on silicon substrates.

The buckyball process initially will be used for hardening silicon micromachine parts against high-temperature or corrosive environments. For example, the silicon membranes employed in microscopic pressure sensors can be coated with silicon carbide to toughen them for use inside internal-combustion engines.

Intel's Grove calls for improved PC architecture

By Rick Boyd-Merritt

Las Vegas -- Calling for an improved PC architecture, with multimedia and communications functions on the motherboard, Andrew Grove has challenged the industry to develop a "looking-glass" computer that would act as a portal between the analog world and the digital realm of cyberspace networks. The president and chief executive officer of Intel Corp. threw down the gauntlet in his Comdex/Fall keynote address last week.

Grove's vision was praised by some industry observers as a killer of key design bottlenecks, but assailed by others as Intel's latest attempt to broaden its already extensive PC franchise.

The cornerstone of Intel's competitive thrust as outlined by Grove is the Native Signal Processing (NSP) initiative, which seeks to add multimedia and communications functions to the Pen tium. Addition of a low-end codec to the motherboard would permit software-based 16-bit wavetable sound synthesis and video decompression. Chip sets planned by Intel's PCI Components Division and others would accelerate NSP traffic via Peripheral Component Interconnect (PCI) local-bus links to deliver sustained 100-Mbit/second data transfers and enhanced IDE-bus mastering in core logic. The first chips are believed to be slated for January and will target a 120-MHz spin of the P54C Pentium.

Samsung sets transition to 12-inch wafers

By David Lammers

Tokyo -- The 12-inch-diameter wafer is expected to be crowned as the next generation's standard format, after a Nov. 29 summit of Asian, European and U.S. semiconductor groups. They will meet in Tokyo under the auspices of Semiconductor Equipment and Materials International (SEMI) prior to the Semicon Japan '94 show.

But some manufactur ers are jumping the gun. Samsung Electronics will begin using 12-inch wafers in 1998 for second-generation 64-Mbit DRAMs, well ahead of most other DRAM makers' schedules, which call for use of the large-diameter wafers for 256-Mbit DRAMs by 2000 or later (see Oct. 10, page 4) . Motorola Inc. is also said to be pushing the transition hard--aiming for 12 inches in 1998--so that its PowerPC microprocessor's price can pace Intel's Pentium.

The move to 12-inch wafers will require more than a road map. Processing equipment will have to be changed, requiring new tooling and standards. Issues of basic physical chemistry, involving the huge wafers' behavior at high temperatures, also must be resolved. When many of the same issues plagued the shift to 8-inch wafers, IBM Corp. spent an estimated $2 billion with U.S. equipment companies to codevelop processing equipment for that generation. This time around, it will likely be Samsung, Motorola and Intel Corp. that will drive their vendors' equipme nt development.

Europeans team for on-chip bus standard

By Peter Clarke

Dublin, Ireland -- Opening the door to modular and reusable designs, five of the biggest European semiconductor vendors have defined an on-chip synchronous, parallel bus that will permit development of a standard European library of ASIC cells.

The peripheral internal bus--PI-Bus--was developed by Advanced RISC Machines (Cambridge, England), Matra MHS (Nantes, France), Philips Semiconductors (Eindhoven, the Netherlands), SGS-Thomson Microelectronics (Agrate, Italy) and Siemens Semiconductors (Munich, Germany). The work was done under Europe's Open Microprocessor Systems Initiative and was disclosed at an OMI conference here.

The bus, which supports data paths up to 32 bits wide, can connect any two on-chip functional units and allows multiple masters. It also supports protocols for acquiring and relinqu ishing control, handshaking and testing.

Matra will release its first chip using the PI-Bus in 1995. It will connect to peripheral units only, because a very-high-bandwidth path is needed to connect the main CPU to memory.

The bus is being made available to ASIC-cell developers as a tool kit that describes the protocol and can be used for testing. The kit includes the technical specification, a behavioral VHDL model that can be used for synthesis, and simulation code that can be used to check conformance with the standard.

Kodak researchers aim to take error correction mainstream

By Ron Wilson

Berkeley, Calif. -- Most designers think of Reed-Solomon error correction--if they've heard the term at all--as an arcane part of the mysterious insides of disk-controller chips. But work under way at a tiny storefront a few blocks from the University of California campus could soon catapult Reed-Solomon to prominence.

There, Kodak Berkeley Research (KBR) engineers have perfected a unique blend of applied mathematics and systems engineering that promises to make the decades-old technique a mainstream tool of the communications society.

The way KBR systems engineering manager Jerry Walker explains it, "The simplest approach to noise in data communications is to detect errors in the receiver and just ask for retransmission--what we call an automatic request for retransmission." But there are places where that isn't practical, he said, such as broadcast, long-latency links and very noisy environments.

That is the domain of forward error correction (FEC), which involves fixing the errors at the receive end rather than asking for another copy of the data. But as the industry increasingly tries to stuff error-sensitive data types--numeric data, compressed video and the like--through narrow and noisy channels, that domain is expanding. Hence, like spread-spectrum communi cations (with which it has been closely linked), FEC is being drawn into the mainstream. And with FEC comes the most powerful tool in its arsenal: Reed-Solomon error correction.

It is the freedom to manipulate all of the variables in the system--from the space in which the algebra is done to the choice of polynomial to the partitioning between hardware and firmware to the decision to take analog input from an automatic-gain-control circuit--that makes Reed-Solomon such a powerful technique, according to Walker.

And, he argues, it is the unique situation of KBR, suspended as it is between the applied-mathematics world of the Berkeley campus and the rolled-up sleeves of Silicon Valley, that gives the company the power to manipulate all the variables.

Open Set-top group plans modular architecture

By Michele Clarke

Las Vegas -- Will a standard from the Video Electronic Standard s Association (VESA) finally create convergence in the TV set-top box community? Judging from last week's industry reaction to news that one was about to be issued, don't hold your breath.

The standard due early next year from VESA's Open Set-top alliance could be implemented on a set-top box, inside a digital television or as a PC add-in card. But development managers from Apple Computer Inc., General Instrument and Stellar One Corp. said they'd like the VESA committee to define a vendor-independent network-interface module and standard communication protocol--and leave underlying hardware decisions to them.

"The hardware is the least of our problems," said Paul Budak, chief technical officer of Stellar One.

Disclosing its plans during VESA's regular meeting at Comdex/Fall, the committee said the VOST (for VESA Open Set-top) architecture will break today's highly integrated designs into eight functional blocks: compression/decompression, multiplex processing, data storage, multimedi a output, conditional access (a security feature), and human, home-network and provider interfaces.

Intel outlines Pentium warranty

By Alexander Wolfe

Santa Clara, Calif. -- Intel Corp. officials last week said that owners of Pentiums made prior to an upgrade of the chip's floating-point unit might be able to trade in their microprocessors for a replacement.

The upgrade was made to correct a condition that causes inaccurate results on some high-precision calculations (see Nov. 7, page 1) .

"This has shown up exactly once. It's not an error. It's not an issue in almost any use," said Dennis Carter, vice president of Intel's corporate marketing group. "If customers are concerned--and if the kind of use they're putting their computer through is remotely one where they're likely to see this--then we'll replace [the part]. But, in general, it's not an issue, so th ere's no replacement."

Intel said that customers could contact its technical support department at (800) 628-8686.

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