RF synthesis is a critical function in today's electronic communications systems. Two of the technologies used for RF synthesis are phase locked loop (PLL) and direct digital synthesis (DDS). Each has its relative strengths and shortcomings.
A PLL is a closed loop system in which the stability of the feedback loop is of paramount importance. The system settling time is very much dependent on the characteristics of the closed loop system. A DDS, which is an open loop system, has a nearly instantaneous response time and therefore has no settling time or stability concerns.
PLL based synthesizers are capable of generating frequencies well into the GHz range, with low power consumption. On the other hand, DDS based synthesizers are noted for their tuning resolution, frequency sweeping and fast hopping, while being somewhat more demanding in power requirements. Also, DDS ICs capable of producing frequencies in the hundreds of MHz have been relatively late in appearing. Each method of frequency synthesis has applications where it shines above the other.
Both PLLs and DDSes require a reference frequency in order to operate. In the case of PLLs, the reference frequency is usually only a fraction of the desired output frequency.
There are two categories of PLL implementation integer n and fractional n that allow for different ways of determining the tuning resolution and other aspects of PLL operation. A PLL based system requires a voltage controlled oscillator (VCO), which is usually a separate device whose performance is crucial. The RF output from a PLL/VCO is a continuous time analog signal.
DDSes require a reference clock, which must be more than 2x the highest frequency output available from the DDS in its fundamental range. Some DDS ICs incorporate on chip clock multipliers (often implemented by PLL), thereby allowing the designer the option of using a lower frequency reference on board. The output of a DDS is a discrete time sampled sine wave of a frequency determined by the digital core of the DDS as a result of the frequency tuning word and reference clock frequency. The sampled sine wave output of the DDS must be low pass filtered by a suitable reconstruction filter to provide a proper analog RF signal.
Many of today's communications devices and systems call for RF synthesizer performance, which may be difficult or impossible to implement using PLL or DDS alone.
To achieve both the frequency range and other system requirements of these ever more demanding applications, system designers often tackle such tasks by using a combination of PLL and DDS technologies. The strengths of one technology join those of the other technology to extend the possible range of performance available to the RF system designer.
One of the most critical requirements in RF synthesis systems is to achieve and maintain low phase noise. All of the many contributors to phase noise should be minimized if maximum system performance is to be achieved. Phase noise, no matter how low in the primary frequency component, grows with increasing frequency multiplication or with PLL frequency gain in a complete synthesizer.
One of the ways in which PLL and DDS technologies can join forces is by allowing the design of synthesizers that simultaneously achieve the goals of high frequency output, fine tuning resolution and fast settling time, along with low phase noise.
There are various ways in which PLL and DDS devices can be combined to produce an RF synthesizer that goes beyond the capabilities of either technology alone. Introductions to several of these architectures are given in the full presentation for this week's Communications Design Conference (CDC). Here there is only space to mention one, and to discuss some of the ways in which the architecture advances the task of achieving the desired performance level. This architecture is shown in the illustration.
In the synthesizer architecture shown, there are several techniques that are used to capitalize on the capabilities of both PLL and DDS. This particular circuit does not attempt to minimize components or cost. The complete presentation shows other circuit arrangements that are simpler. This example, however, includes several techniques that can optimize phase noise performance.
First, the two LOs would most likely be implemented as fixed frequency PLL loops. Fixed PLL loops can be highly optimized for phase noise within the loop bandwidth by the design of the loop filter and outside the loop bandwidth by careful choice of the VCO. In addition, the quality of the DDS clock should be as high as attainable, because this source directly determines the phase noise performance of the DDS.
The low pass filter following the DDS is required in order to reconstruct the DDS' time sampled sine wave output. The mixer and LO1 serve to translate the DDS output up in frequency without multiplication or frequency gain, thereby serving to preserve the phase noise performance of the DDS itself, without increasing the tuning step size of the DDS. The bandpass filter following the mixer is needed to select the desired frequency, as well as to help filter the wideband noise that may be present at that point.
Reducing phase noise
The divider following the bandpass filter divides down the DDS output frequency to apply the reference input to the phase detector. This division significantly reduces the level of any spurs in the DDS spectrum, thereby reducing phase noise and jitter in the overall loop. The PLL loop that serves as the output of the synthesizer operates as a translation loop, in which the VCO output is mixed down, rather than divided down, to close the loop at the phase detector. Again, the frequency gain of the loop is kept at unity, thereby avoiding the consequent growth in phase noise that would occur with increased frequency gain. The increase in phase noise that is expected from frequency gain is given by 20log(N), where N is the frequency gain of the loop.
The block diagram in the illustration on page 59 combines DDS and PLL in such a way that the fine tuning capabilities of the DDS are added to the multi gigahertz output capability of the PLL/VCO to achieve a high performance RF synthesizer with excellent phase noise. Other optimizations can be made according to the demands of the overall system and the specific requirements of the frequency synthesis subsystem.
Pascal Nelson (Pascal.Nelson@analog.com) is an applications manager within the Clock and Signal Synthesis Products group of Analog Devices Inc. (Greensboro, N.C.).
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