Atmel's AVR32 UC3 core targets ARM7/9 and Cortex-M3 sockets

The AVR32 UC3 core delivers up to 1.3 Dhrystone MIPS/MHz while running from on-chip flash. Atmel reports that this is the only 32-bit RISC core in this size range to include single-cycle DSP instructions. Additionally, the company also reports that it is the first core in the industry to integrate single-cycle read/write SRAM with a direct interface to the CPU that bypasses the system bus. This was designed to achieve faster execution, cycle determinism, and lower power consumption.

The core features high-speed bus (HSB) slave interface access, which allows DMA controllers or other HSB masters to write to or read data directly from the SRAM. Arbitration is performed if the CPU and a high speed slave request access simultaneously. The priority scheme is programmable to suit different applications.

The AVR32 UC3 core includes power management functions, a memory protection unit (MPU), and a 32-bit single-cycle access flash interface. It also features a 6-level priority interrupt controller including non-maskable interrupt (NMI) with fast event handling, and a three stage pipeline that does not require instruction or data caches, data forwarding, hazard detection or branch prediction.

The AVR32 UC3 core shares the same instruction set architecture (ISA) as the AVR32 AP , with more than 220 instructions available as 16-bit compact and 32-bit extended instructions. The AVR32 ISA is designed to minimize data transactions between the core and memories, saving both power and clock cycles. The compiler automatically selects the most efficient compact or extended form of the each instruction.

The UC3 instruction set includes atomic instructions to manipulate mutexes and semaphores, and for general bit-manipulation. The UC3 core includes on-chip RC oscillator as the main clock source. An on-chip power-on reset and brown-out detector ensure device operation over the guaranteed power supply voltage range. A memory protection unit (MPU) controls memory allocation and manages access privileges. The MPU allows restriction of read / write / execute access to different memory areas depending on the privilege mode.

Atmel reports that the AVR32 UC3 code is consistently 5% to 20% smaller than code compiled for the ARM Thumb® instruction set. And, when code is optimized for execution speed, AVR32 UC3 code is 30% to 50% more compact than code compiled for the ARM instruction set.

Atmel Corp.
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