ARCHITECTURES: Multimedia platform stresses flexibility

Shanghai, China -- ARC International is laying a new foundation for a scalable multiprocessor architecture that will exploit parallelism to chew through compute-intensive tasks like high-definition encoding and decoding. At the same time, it will be flexible enough to slim down for low-power, portable designs that need only do simple decode of MP3 and standard-definition video.

The first implementation of ARC's VRaptor Media Architecture is actually its ARC Video platform, released in February. It supports an ARC 700 family core with a single-instruction, multiple-data (SIMD) accelerator and DMA engine.

The second implementation of the VRaptor, which uses a 750D CPU, will come in early 2007, when ARC extends support to include H.264 encoding at standard definition and the pairing of multiple CPUs, SIMD engines and hardware accelerators. From there, ARC will likely move to high-definition decode, followed by HD encode. It's at this later point that designers will really begin to leverage parallelism to increase performance while keeping a cap on power consumption.

The SIMD accelerator was developed to exploit the data parallelism inherent in media applications, with a single instruction able to compute up to eight separate 16-bit video pixels simultaneously via a 128-bit-wide data path. Supported codecs include H.264, MPEG-4, MPEG-2 and VC-1, as well as image files. ARC will also provide architectural licenses and tools to allow customers to design their own multiprocessor architectures and map media-processing software to the resulting processor arrays.

The scalability of the architecture will interest designers of large video systems, such as TVs and set-top boxes, as well as those doing compute-intensive portable devices. Designers in the first group will benefit by being able to knit together a control CPU with a string of multiple SIMDs that would handle the pixel-intensive processing. Such a cluster would be linked with a 32-bit-wide, point-to-point active communications channel architecture.

A simpler implementation might see a system doing H.264 encoding, using a 750D linked to one media processor (SIMD) for pixel transforming and to another media processor for deblocking. The CPU would also link to hardware accelerators for motion estimation and entropy encoding.

"Or, for video encoding and decoding applications, there is a lot of decision making that has to be done along the way, and that's best done in a RISC processor. So in those types of applications, multiple RISCs will be advantageous," said Jonah Probell, director of ARC's video development.

The VRaptor needs 200 MHz for SD H.264 encoding. The SIMD array present in the ARC Video is software-programmable, so it acts as the media processor, capable of handling media operations such as deblock filters, pixel transforms and audio processing. The programmability will let developers introduce proprietary algorithms for product differentiation.

The VRaptor architecture is expected to scale from simple MP3 decode to complex HD H.264. Developers should be able to keep clock frequencies down to a few hundred MHz, or even reduce clock frequency if the processing load is spread across more processors, said Peter Hutton, senior vice president of engineering at ARC.

--Peter Clarke of EE Times Europe contributed to this story.