Synopsys adds physical guidance to topographical technology

Synopsys (Mountain View, Calif.) said it has extended its topographical technology in Design Compiler 2010 to produce physical guidance to its place-and-route solution, IC Compiler, delivering a significant decrease in iterations and reducing run times in physical implementation.

More specifically, Synopsys noted that timing and area correlation are reduced down to 5 percent. Additional physical optimization techniques are applied during synthesis, and physical guidance is created and passed to IC Compiler, streamlining the flow and speeding up placement in IC Compiler by 1.5 time.

In addition, Synopsys' Design Compiler 2010 provides RTL designers with an access to IC Compiler's floorplanning capabilities within the synthesis environment.

Design Compiler 2010 also includes a scalable infrastructure that is claimed to achieve runtime speedup on multicore compute servers. It uses a scheme of distributed and multithreaded parallelization techniques, delivering about 2x faster runtime on quad-core compute servers while achieving zero deviation of the synthesis results, the company claimed.

In 2008, Synopsys also extended Design Compiler topographical technology with the introduction of Design Compiler Graphical synthesis product aimed at helping RTL designers avoid wire-routing congestion problems that occur during detailed route.

Design Compiler Graphical predicts circuit congestion "hot spots" early in the design flow, provides designers with visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in these areas, the company then claimed.