Lattice FPGA design suite adds support for DDR interfaces

SAN FRANCISCO—Lattice Semiconductor Corp. Tuesday (Nov. 9) announced Version 8.0 of its ispLEVER FPGA design tool suite, which the company said includes enhancements for the design of high-speed double-data-rate (DDR) interfaces for the LatticeECP3 FPGA family.

According to Lattice (Hillsboro, Ore.), these enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details. Lattice's IPexpress tool now can generate the HDL for the most appropriate generic DDR interface based on user requirements such as direction, speed and bus width, Lattice said. This HDL has been designed and validated for high performance, robust operation, the company said. For the ECP3 family, certain DDR interfaces can now be implemented with much higher pin layout flexibility, according to the company.

The Trace static timing analysis report has been enhanced to include a "Timing Rule Check" section that specifically analyzes these clock domain transfers, Lattice said. This is done automatically and does not require users to define additional timing constraints, the company said.

The IPexpress tool can now also optionally generate the complete I/O-specific circuitry for proprietary DDR memory interfaces, allowing designers to focus solely on the controller logic of their DDR1 and DDR2 DRAM interfaces, Lattice said.

Improvement in place-and-route algorithms enable ispLEVER 8.0 software to complete large, congested designs 30 percent faster than with the previous ispLEVER 7.2 SP2 release, according to Lattice.

Lattice said it also continues to enhance and expand support for the open source 32-bit RISC LatticeMico32 ecosystem. The GNU compiler has been upgraded to Version 4.3.0, which enables higher system performance and more flexible code deployment options, Lattice said. The Tri-speed MAC IP can now be interconnected into higher throughput configurations, the company said, and the component library now includes a dual port on-chip memory to enable high speed information passing between Wishbone bus masters, and an enhanced SPI Flash Controller allows both read and write access.

The ispLEVER 8.0 tool suite for Windows, Linux and Unix users is available immediately without charge for customers with active design tool maintenance contracts, Lattice said. Pricing for the full ispLEVER design tool suite starts at $1,295 for the Windows version, the company said.