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resistion
First sentence suggests Samsung at 19 nm, but actually they should be ...
dylan.mcgrath
Yes, you are correct. ...
Memory firms detail sub-20-nm NAND chips
Dylan McGrath
2/23/2012 12:42 AM EST
SAN FRANCISCO—Engineers from Samsung Electronics Co. Ltd., Toshiba Corp. and SanDisk Corp. took to the podium to provide details of their respective 19-nm NAND flash chips in presentations at the International Solid-State Circuit Conference (ISSCC) here Wednesday (Feb. 22).
Samsung's Daeyeal Lee delivered a paper describing the company's 64-Gbit multi-level cell (MLC) NAND device implemented in sub-20-nm technology. The device features a 533-megabit-per-second DDR interface achieved by implementing a wave-pipeline architecture, Lee said. The chip also makes use of new techniques to overcome floating-gate coupling interference and mitigate program disturbance, Lee said.
According to Lee, the use of the new schemes, known as correction-before-recoupling reprogram and P3 pattern pre-pulse scheme, results in a 21 percent lower bit error rate compared with conventional techniques. Lee described another technique, inhibit-channel-coupling-reduction, for mitigating program disturbance in the chip.
A bit of controversy erupted at the end of Lee's presentation, when one audience member, who identified himself as a member of conference's memory subcommittee, chastised Lee for declining to describe the size of memory cell size of the chip, suggesting that Samsung was not providing enough information for an ISSCC paper.
Earlier Wednesday, Toshiba's Noboru Shibata described his company's 19-nm multi-level 64-Gbit NAND device. Shibata said the chip's die size is 112.8 square millimeters, the smallest ever reported for a NAND flash device.
According to Shibata's presentation, the Toshiba chip, which was developed under its long-standing collaboration with SanDisk, achieves an industry first with 15-megabyte-per-second programming throughput. The device employs a one-sided, all-bitline architecture and single-array configuration, he reported. The chip also employes a high-speed toggle-mode interface, he reported.
Asked to comment on the write cycle endurance of the device—an increasing concern as chip makers shrink the feature sizes of NAND—Shibata said it was equivalent to Toshiba's 24-nm NAND. Shibata's presentation described the implementation of a new memory cell programming algorithm meant to mitigate program disturbances.
Also Wednesday, Yan Li, director of memory design at SanDisk, presented a paper on SanDisk's 19-nm, 128-Gbit monolithic device that stores 3-bits per memory cell, the highest density IC ever produced.
Samsung's Daeyeal Lee delivered a paper describing the company's 64-Gbit multi-level cell (MLC) NAND device implemented in sub-20-nm technology. The device features a 533-megabit-per-second DDR interface achieved by implementing a wave-pipeline architecture, Lee said. The chip also makes use of new techniques to overcome floating-gate coupling interference and mitigate program disturbance, Lee said.
According to Lee, the use of the new schemes, known as correction-before-recoupling reprogram and P3 pattern pre-pulse scheme, results in a 21 percent lower bit error rate compared with conventional techniques. Lee described another technique, inhibit-channel-coupling-reduction, for mitigating program disturbance in the chip.
A bit of controversy erupted at the end of Lee's presentation, when one audience member, who identified himself as a member of conference's memory subcommittee, chastised Lee for declining to describe the size of memory cell size of the chip, suggesting that Samsung was not providing enough information for an ISSCC paper.
Earlier Wednesday, Toshiba's Noboru Shibata described his company's 19-nm multi-level 64-Gbit NAND device. Shibata said the chip's die size is 112.8 square millimeters, the smallest ever reported for a NAND flash device.
According to Shibata's presentation, the Toshiba chip, which was developed under its long-standing collaboration with SanDisk, achieves an industry first with 15-megabyte-per-second programming throughput. The device employs a one-sided, all-bitline architecture and single-array configuration, he reported. The chip also employes a high-speed toggle-mode interface, he reported.
Asked to comment on the write cycle endurance of the device—an increasing concern as chip makers shrink the feature sizes of NAND—Shibata said it was equivalent to Toshiba's 24-nm NAND. Shibata's presentation described the implementation of a new memory cell programming algorithm meant to mitigate program disturbances.
Also Wednesday, Yan Li, director of memory design at SanDisk, presented a paper on SanDisk's 19-nm, 128-Gbit monolithic device that stores 3-bits per memory cell, the highest density IC ever produced.
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toom_tabard
2/23/2012 11:40 AM EST
Didn't Micron already announce a 128Gbit single chip a few weeks ago?
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dylan.mcgrath
2/23/2012 3:05 PM EST
Yes, you are correct. http://www.eetimes.com/electronics-news/4231138/Intel-Micron-128-Gbit-NAND-flash-memory
Supposed to be in production in the fist half of this year....
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resistion
2/26/2012 4:55 AM EST
First sentence suggests Samsung at 19 nm, but actually they should be transitioning from 21 to 16 nm.
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