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D2S tips mask-wafer double litho simulator
Dylan McGrath
9/20/2011 12:01 PM EDT
SAN FRANCISCO—Computational design platform vendor D2S Inc. Tuesday (Sept. 20) rolled out a mask-wafer double simulation accelerated workstation for chip designs featuring linewidths of 20-nm and below.
According to Aki Fujimura, D2S chairman and CEO, the company's TrueMask mask-wafer simulation platform is a first of its kind. Traditionally, he said, lithography simulation has focused more heavily on the wafer than the photomask, with the assumption that the mask writing was accurate enough.
"It's no longer the case that you can make that assumption going into 20-nm and beyond because mask features now that you have to write on a mask are 80-nm and below," Fujimura said. "It so happens that because of the physics, 80-nm is kind of a magic number."
Fujimura said TrueMask is more evolved than simple simulation, providing instead "a complete platform for exploration for understanding designs and exactly how they will transfer to a wafer during lithography.
According to Naoya Hayashi, a research Fellow at photomask vendor Dai Nippon Printing Co., sub 80-nm mask features occur frequently at 20-nm logic nodes and below and require increasingly sophisticated technologies to print accurately on a mask.
"Of particular interest are sub-resolution assist features (SRAFs) and other small features that decorate the mask to improve wafer quality," Hayashi said. He added that chip makers are interested in making balanced cost-benefit trade-offs between the wafer quality achievable with techniques such as complex optical proximity correction (OPC), inverse lithography and source-mask optimization.
"An interactive mask-wafer double simulation would enable efficient exploration of these trade-offs for critical circuits," Hayashi said.
Lithographers have for years been using OPC to add SRAFs to photomasks to compensate for the optical effects of sub-wavelength lithography that prevent small features from printing correctly. At the 20-nm node and beyond, the shapes of these SRAFs as well as main features must become more complex to produce the desired images with sufficient process window on the wafer, Fujimura said. This added data causes mask write-times to skyrocket, he said.
Once SRAFS shrink to below 80 nm in size, there is no longer a guarantee that they can be reproduced as desired on the photomask due to the combination of short-range blur of the electron beam used to write the masks and the effects from the mask develop, bake and etch processes, according to Fujimura.
"The reality of 20-nm design is that now you have to make tradeoffs between what's good for the mask and what's good for the wafe," Fujimura said. "What's good for the maks is what can practically be written in reasonable write time. What's good for the wafer is good yield."
TrueMask DS leverages hardware acceleration to produce a double simulation of the mask and wafer for 5x5 micron (on wafer) areas at interactive speeds, according to D2S. Users can experiment using different variable-shaped beam shots to write the masks, as well as using overlapping shots and dose modulation—techniques that can be employed to reduce mask write times and improve CD uniformity, respectively, the company said. Then, users can instantly see the contour shape of the exposed resist, and within seconds see an overlay of the lithography aerial image that would be printed on the wafer.
TrueMask DS offers0.1-nm-resolution mask simulation up to 300x300 micron (mask dimensions), including overlapping shots and dose modulation; advanced e-beam modeling with arbitrary point spread functions for exploration; and SEM interface for overlay analysis of pictures with simulations, according to D2S.
The product is available now, D2S said. Pricing information was not provided.
According to Aki Fujimura, D2S chairman and CEO, the company's TrueMask mask-wafer simulation platform is a first of its kind. Traditionally, he said, lithography simulation has focused more heavily on the wafer than the photomask, with the assumption that the mask writing was accurate enough.
"It's no longer the case that you can make that assumption going into 20-nm and beyond because mask features now that you have to write on a mask are 80-nm and below," Fujimura said. "It so happens that because of the physics, 80-nm is kind of a magic number."
Fujimura said TrueMask is more evolved than simple simulation, providing instead "a complete platform for exploration for understanding designs and exactly how they will transfer to a wafer during lithography.
According to Naoya Hayashi, a research Fellow at photomask vendor Dai Nippon Printing Co., sub 80-nm mask features occur frequently at 20-nm logic nodes and below and require increasingly sophisticated technologies to print accurately on a mask.
"Of particular interest are sub-resolution assist features (SRAFs) and other small features that decorate the mask to improve wafer quality," Hayashi said. He added that chip makers are interested in making balanced cost-benefit trade-offs between the wafer quality achievable with techniques such as complex optical proximity correction (OPC), inverse lithography and source-mask optimization.
"An interactive mask-wafer double simulation would enable efficient exploration of these trade-offs for critical circuits," Hayashi said.
Lithographers have for years been using OPC to add SRAFs to photomasks to compensate for the optical effects of sub-wavelength lithography that prevent small features from printing correctly. At the 20-nm node and beyond, the shapes of these SRAFs as well as main features must become more complex to produce the desired images with sufficient process window on the wafer, Fujimura said. This added data causes mask write-times to skyrocket, he said. Once SRAFS shrink to below 80 nm in size, there is no longer a guarantee that they can be reproduced as desired on the photomask due to the combination of short-range blur of the electron beam used to write the masks and the effects from the mask develop, bake and etch processes, according to Fujimura.
"The reality of 20-nm design is that now you have to make tradeoffs between what's good for the mask and what's good for the wafe," Fujimura said. "What's good for the maks is what can practically be written in reasonable write time. What's good for the wafer is good yield."
TrueMask DS leverages hardware acceleration to produce a double simulation of the mask and wafer for 5x5 micron (on wafer) areas at interactive speeds, according to D2S. Users can experiment using different variable-shaped beam shots to write the masks, as well as using overlapping shots and dose modulation—techniques that can be employed to reduce mask write times and improve CD uniformity, respectively, the company said. Then, users can instantly see the contour shape of the exposed resist, and within seconds see an overlay of the lithography aerial image that would be printed on the wafer.
TrueMask DS offers0.1-nm-resolution mask simulation up to 300x300 micron (mask dimensions), including overlapping shots and dose modulation; advanced e-beam modeling with arbitrary point spread functions for exploration; and SEM interface for overlay analysis of pictures with simulations, according to D2S.
The product is available now, D2S said. Pricing information was not provided.
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