The StarPro 2000"DSP-System-On-Chip

Ray Weiss
DSPnet Site Director

Lucent’s StarPro is the first true, fourth generation DSP system-on-chip. Designed for DSP MP performance, it integrates three StarCore VLIW DSP processor cores with 768-KB of on-chip main memory and peripherals. Running at 300-MHz, this DSP SoC can deliver a peak of 3600 MMACs performance with a typical power dissipation of only 1.5-W.

Unlike most SoCs, this chip builds on a systems bus—the Daytona bus. This bus is not a revamped processor main bus, but a true systems bus with arbitration. It is also a split-transaction bus, one that splits the transaction request and address from the transaction data access. The bus incorporates address and data buses, which can be arbitrated for separately or as a whole transaction.

What ties the on-chip processors, memory, and peripherals together is the on-chip Daytona bus. This is a true systems bus, not just another revamped processor main bus, as is the case with most SoCs. And this bus supports full multiprocessing operations with the three on-chip DSP processors, as well as with the chip peripherals and on-chip memory. The bus provides an efficient mechanism for address-based interchanges between the different chip elements. It is a split-transaction bus with separate address and data buses that can be arbitrated for as separate resources.

To interface with the bus, the DSP processors are encapsulated in what Lucent calls a SuperCore. This is an IP module that integrates the DSP with its support silicon and interfaces to the bus. The StarCore SuperCore integrates the StarCore DSP with 8-KB of instruction and data caches, as well as 16-KB of local DSP memory and the Daytona bus interface. When the DSP needs to access main memory it does so via the Daytona bus. The bus is a universal or general bus, and the DSPs are just another device to the bus, although they can be assigned a higher priority and are transaction initiators. Interchanges between DSP SuperCores are also via the bus. One DSP can Read/Write another DSPs local memory. In addition, the bus supports messaging as well as broadcasting.

The chip incorporates peripherals to handle TDM and packetized data flow traffic. The chip has three Serial I/O Units, or SIOs. These can link the chip to a TDM highway or to other DSP processors. Each SIO provides a Snyc, a Clock, and a Data line.

In addition, the chip has a Parallel I/O Unit that provides a 31-bit address and 32-bit data interface to external peripherals or coprocessors. This interface provides a glueless connection to the Motorola PowerQUICC communications controller. This is a passive parallel port has flexible addressing modes and buffering to minimize the need for interface glue logic.

StarPro provides two external memory ports to external memory and peripherals. The two external Memory Interface Units (MIUs) provide a 32-bit interface (31-bit address, 32-bit data), thus, the chip supports hierarchical memory, running from DSP caches, DSP local memory, to chip main memory, to two sets of external, off-chip memories. The chip architecture also incorporates eight memory-to-memory DMA channels (MMTs). These DMA engines support block memory transfers from or to anywhere in the chip's memory space.

StarPro 2000 Architecture and Key Features
DSP system-on-chip Three 16-bit, fixed-point StarCore DSPs StarCore DSP is six-issue VLIW Four MAC/ALU/Shift Units per StarCore Three StarCore Macrocells, each has: One StarCore DSP processor 8-KB I, D caches 16-KB DSP local memory Local JTAG-based debug port 768-KB local unified memory (accessed via bus) Daytona bus—memory mapped Split-transaction, ID-based, synchronous bus 32-bit address and 128-bit data buses User programmable arbitration Three Serial I/O Units (SIO)—Full-duplex, double-buffered port Programmable control of frame and bit clock Two 32-bit External Memory Interface Units (MIU) One Parallel Interface Unit (PIU) 32-bits data, 31-bit address Two Bit I/O (BIO) units—each controls eight digital I/Os Six 32-bit timers.	System clock is 300-MHz DSPs, Daytona bus run at 300-MHz StarCore DSP Can issue two address, four MAC/ALU/Shift instructions/cycle Delivers 1200 peak MMACs per DSP Delivers 3600 peak MMACs per chip (three DSPs) Main Memory has two cycle latency Pipelined to deliver apparent one cycle reads Daytona bus runs at DSP clock rate Designed for single, or short-burst accesses Central arbiter Arbitrates for address bus, data bus, or address and data buses Address and data buses can operate concurrently on different transactions Registered operation, no signal turnarounds Serial I/O Units Support T1/E1 connections 50-Mbits/sec per channel for whole 128 channel frame 20-Mbits/sec per channel for 32 channels in a frame Two DMA channels/SIO to DSP memory space 1.5-W typical @ 1.5-V 3.3-V or 2.5-V I/O, 516-pin PBGAM LuxWorks Lucent development environment.

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