DSPs Repeating History

History, as philosophers have noted, tends to repeat itself. The DSP world is no exception. Microprocessors quickly gave way to DSPs, and like their microprocessor ancestors, DSPs are now on a fast track to change.

Starting from the early days, the microprocessor arena was dominated by a few key architectures that became de facto standards: the 6805 (and antecedents), the 8051, the 68000, and the X86. These architectures dominated early designs, contributing to a large code base.

Today, early micro standards such as the 68xx and the 8051 are under assault from competitors like Microchip's PIC, some RISC 8-bitters, and a raft of peripheral-rich 8-bitters. Similarly, the 68K, king of 32-bit micros, is losing ground to newcomers like MIPS, ARM, and SH-series.

For awhile, it looked as if the faster RISCs would take over, subbing for slower CISC DSPs. That didn't happen—DSPs were not dinosaurs run over on the evolutionary track. Fourth generation and beyond DSPs incorporate a mix of processor technologies including RISC (superscalar and pipelining), SIMD, MP, MP Arrays, extended and configurable instruction sets, and VLIW processing.

Embedded system designers are now looking beyond DSPs to other architectures that will better address issues such as:

• Shifts to high-level language (C)
• Moves to single chip solutions with special on-chip peripherals
• Requirements for more performance
• Need for more architectural and deployment variation.

Similarly, DSPs have moved beyond the core architectures that dominated almost 10 years of intense growth. DSPs are no longer CISC machines that can competently handle series (e.g., access an operand and constant, multiply them, and accumulate the result). Today's 4th generation DSPs have gone from stick-in-the-mud, optimized CISC machines to today's leading edge CPU architectures. These machines include wide-word VLIWs (TI's C6x, the 1st successful commercial VLIW), multiple path SIMDs, superscalar RISCs, extensible instruction sets, and more. No slowpokes, DSPs have clock rates pushing 200, 400 MHz and rising, delivering GigaOPS performance.

Silicon Driver

The same combination of architectural innovation with a silicon boost that is driving DSPs has kicked micros into high gear. Silicon technology reached a point where it changed the architectural equations to allow new architectures to enjoy a performance and efficiency boost. RISCs emerged because with higher silicon densities and speeds, the better tradeoff was to reduce the register-ALU-register cycle (with simpler instructions) and trade in microcode for fast cache.

Likewise, DSPs are shifting from fixed CISC operations to more open, programmable operations with wider silicon options. Instead of one instruction generating n CISC operations, you can use VLIWs that specify n instructions per clock cycle. Or try SIMD techniques, where one instruction will do an operation on n parallel fields. You can also deploy superscalar techniques with multiple functional execution units pipelined for fast operation.

Nice capabilities, but silicon still trumps architecture. Silicon relentlessly drives the underlying DSP technology, roughly doubling functionality, capacity, or capability every 18 months. Rising silicon densities and clock rates let designers pack more processors and more functions onto a single chip, resulting in SOCs, multiple DSPs in an MCM, and innovative multi-processor cores like BOPS, Tensilica, and Systolix. Similarly, today's FPGA speeds and densities let designers put DSP processing—soft IP and hardwired logic—right onto the incoming signal stream.

DSPs have indeed repeated microprocessor history. However, we can't look any longer to micros for guidance. DSPs have caught up and are now breaking new architectural trail, but silicon is driving.