Reducing Power Early in the Design Flow

The dynamics of deep submicron, system-on-chip (SoC) design has made power usage an increasing important concern. As the design of power-sensitive products accelerates, so does the need for the design software that can help designers estimate and reduce the power consumed by an integrated circuit (IC) early in the design cycle.

While power consumption can be minimized at each level of abstraction—architectural, logical, and physical—the potential for minimization diminishes as the design becomes more detailed.

Like most trends, integrated circuits (ICs) have grown so big and so fast that the power dissipated during their operation cannot safely be ignored. Design teams contend with the impact on system power planning, on the packaging and cooling infrastructure, and on the power-and-ground network, which must pipe current to the actual silicon devices.

Market trends compound the issue. Fast-growth markets like consumer multimedia, Internet infrastructure, and wireless communications are among the most likely to have products with power concerns. The general shift from application-specific integrated circuits (ASIC) to application-specific standard parts (ASSP) also contributes. An ASIC is locked into a dedicated system—if the chip exceeds its power budget, the designer can often negotiate an allowance from the system architect.

However, the same over-power chip, designed as an ASSP for multiple customers, may well lose business—those customers with power concerns may leave, reducing the overall market for the chip. A similar dynamic applies to intellectual property (IP) cores intended for reuse in multiple SoC ICs.

Lower-voltage silicon no longer provides the relief for power problems it once did. Power usage continues to increase despite silicon technology improvements. The growing use of the same silicon technology means it's less effective for the market problem.

As a result, teams look increasingly to design and design tools as a way to manage power. Function and performance are determined through design, so why not power? Like function and performance, the largest impact on IC power is found early in the design process, at the architectural and register-transfer levels.

Most design teams today handle power the way they handled timing issues—imprecise estimates early in the design, followed by detailed verification just before tape-out. This approach works as long as there is not a problem. Since most of the power in complex ICs is determined in the architecture, by the time the detailed verification finds the problem, it's too late to do anything, except to add fans, heat pipes, or exotic packaging.

At Sente we call this a "cool by assumption" method—if the chip meets its targets, the design team validates its "assumption" that it would do so.

The solution lies at the beginning of the design flow, not the end. Designers need to identify and fix power problems early. What's needed is a design methodology that incorporates power management early—from design concept forward—when changes are inexpensive and don't impact the project schedule. This includes chip-level targets that start during the architectural stage; budgets for individual modules; early estimation and tradeoffs, followed by more refined estimates as the design proceeds; and final verification which doesn't yield surprises. If power-reduction is needed, then the bulk of the design work is spent at the register-transfer level (RTL) or earlier, where the return on effort is still high.

We call it a "cool by design" methodology. Over the last several years, new EDA software has arrived to help designers better estimate and reduce power early in the design flow. In fact, Sente has a suite of RTL power analysis and optimization software designed to do just that. Our goal is to increase a designer's likelihood of hitting the project schedule and cost target by ensuring that excessive power consumption will not be a surprise late in the design cycle. Early knowledge of a design's power characteristics, together with real automation for low power design, enable designers to make design changes and optimizations with minimal schedule impact.

Knowing more about the power consumed by the architecture, designers can explore better micro-architectures and optimize the overall design for minimum power usage. When designers can create lower power designs, they reduce production costs, increase reliability, and offer end-user products that run cooler.