M-LVDS: A New Standard for High-Speed Multipoint Data Buses

	ABOUT THE AUTHOR Jim Dietz is currently responsible for Texas Instruments' new product development in the area of LVDS interface circuits. He has 18+ years experience at Texas Instruments and Raytheon in the area of systems engineering. Jim can be contacted at jimdietz@ti.com.

The demand for moving more data, faster and with less power, is pervasive throughout the electronics industry. The telecommunications and data communications expansion drives the speed of today's communications devices, while component density, reliability concerns, and operational availability necessitate decreased power dissipation. The simultaneous demands to switch faster and consume less power generally lead to multiple design solutions. Designers need new interface technologies to answer today's challenges.

Worldwide standardization groups meet to define, document, and publish electrical-interface standards. There are many benefits of standard compliance. Standards bodies are usually supported by industry experts, leading to incorporation of extensive experience and broad viewpoints into the released publications. Standardization also results in reductions in development costs and cycle time. As silicon vendors provide competing products complying with approved standards, development costs drop. Furthermore, development cycle-time decreases through incorporation of established and proven interface specifications.

A recent addition to the list of available electrical-interface standards is TIA/EIA-644, commonly referred to as LVDS. The Telecommunications Industry Association (TIA) subcommittee TR-30.2 published the standard for Electrical Characteristics of Low-Voltage Differential Signaling (LVDS) Interface Circuits in 1996. The most attractive features of TIA/EIA-644 include its high signaling rate and low power consumption. The standard defines the LVDS electrical-layer characteristics used in transmitting information in point-to-point architectures. While recommending an upper signaling rate of 655 Mbps, the standard allows for signaling rates up to 1.923 Gbps. The high speeds available with LVDS provide opportunities to reduce system cost and increase transmission distance in ways that may not be obvious at first glance. Designers often take advantage of LVDS signaling rates to serialize parallel input data into a single LVDS bit stream, with deserialization performed at the destination end of the transmission link. Numerous serialization and deserialization devices are currently available that utilize LVDS as the means to transfer data across a communication link.

LVDS is seeing rapid acceptance throughout the electronics industry as a replacement for slower-speed, higher-power options such as TIA/EIA-422 or single-ended solutions. LVDS likewise offers a low-power alternative to ECL logic parts when speed is a predominant concern. The one area where LVDS is not a viable alternative is for multipoint applications. The special considerations associated with multipoint operation, as well as the increased drive strength required to supply the heavier loads seen in multipoint designs, requires enhancements to the existing LVDS standard.

The TIA TR-30.2 subcommittee is currently developing the Multipoint-Low-Voltage Differential Signaling (M-LVDS) standard to address the multiple-driver, multiple-receiver, half-duplex problem. The benefits that are familiar to those acquainted with LVDS technology will soon be available for multipoint data transmission.

The original goal of TIA/EIA-644 was to provide a general-purpose electrical-layer specification for drivers and receivers connected in a point-to-point interface. A general-purpose electrical-layer specification should deal with the electrical characteristics present at the physical layer only. A point-to-point interface consists of a single driver and a single receiver, connected by a transmission media. LVDS requires a balanced transmission media of 100- (nominal) characteristic impedance. The transmission media uses a 100- termination impedance to minimize line-end reflections.

LVDS utilizes differential signaling to minimize radiated emissions and to provide robust performance in noisy environments. The standard allows for signaling at rates up to 1.923 Gbps, although the standard also permits lower signaling-rate devices. Current LVDS devices are all designed for operation below 1 Gbps. LVDS-driver outputs have an offset voltage of approximately 1.2 V, with a nominal differential signal of 350 mV. Receivers require input thresholds < 100 mV, while operating in the presence of ±1 V ground shifts. The standard requires receivers to have input leakage currents below 20 µA, which drives the receiver equivalent input-impedance requirement.

A survey of existing LVDS devices shows that many parts exceed the minimum compliance requirements the standard defines. Receivers are available that tolerate ±3 V ground shifts, increasing the distance allowable between driver and receiver, or allowing for operation in environments that are more difficult. Some LVDS receivers require less than the 100mV input signal, providing increased noise margin to the designer.

Although providing a welcome electrical standard for point-to-point transmission, LVDS did not quantify driver performance for multidrop operation. In a multidrop system, one driver is used to interface to multiple receivers. The TIA/EIA-644 receiver leakage requirement of 20 µA has a small effect on driver output voltage when only one receiver is connected, but this effect becomes more pronounced as the driver is loaded with additional receivers. An update to LVDS, designated TIA/EIA-644-A, standardizes the driver requirements for LVDS devices in a multidrop configuration. 644-A adds a full-load test for the driver to ensure that a multidrop configuration can connect up to 32 receivers. It is important to remember that a 644- or 644-A-compliant driver can drive more than 32 LVDS loads, as long as the accompanying receivers have an input resistance greater than 120 k.

The next obvious extension for LVDS technology is design considerations for multipoint operation. Multipoint operation takes off where 644-A ends by allowing for multiple drivers as well as multiple receivers on the bus. Multipoint operation allows for bi-directional, half-duplex communication over a single balanced-media pair. In order to support the arbitrary location of the various drivers throughout the transmission line, double termination of the line is now necessary, again for reflection considerations. The doubly terminated bus increases the load seen by the drivers, resulting in a need for higher output-current drivers. While a multipoint application can use LVDS-compliant drivers, such operation is not a good idea, since it could significantly impair noise margin.

The first step to realize the benefits of LVDS in a multipoint operation is to increase driver output strength. Silicon vendors have already taken this step, and offer high output-current LVDS-like drivers. Texas Instruments offers an LVDM family of drivers, compliant with the 644 LVDS standard with the exception of a doubling of the output current. National Semiconductor offers a Bus LVDS family of drivers that increases the output current of the drivers to approximately 10 mA. While supporting driving loads heavier than 100, these solutions do not provide standard compliance, nor guarantee interchangeability, and therefore may find limited acceptance by the design community. M-LVDS builds on these interim multipoint solutions, and brings the benefits of standardization to the application of LVDS in a multipoint design. Numerous multipoint standards already exist, so before looking at what will be offered by M-LVDS, a brief review of these standards is useful.

Single-ended multipoint solutions are present in many existing designs. TTL and CMOS logic circuits are common, but suffer from high voltage swings and large drive requirements. Backplane transceiver logic (BTL: IEEE 1194.1) and Gunning transceiver logic (GTL) are single-ended standards that operate with reduced voltage swings (BTL at 1.1 V, GTL at 0.8 V). GTL-plus (GTLP) is an enhancement of GTL, offering pre-charge circuitry to support live insertion, as well as increased current for heavily loaded backplanes. Although single-ended solutions are the right answer for numerous design challenges, they are not the correct choice with extended line lengths or high signaling rates (>100 M-transfers/sec). Single-ended transmission is also susceptible to performance degradations when exposed to environmental noise, and generally provides little tolerance to ground shifts between driver and receiver.

The most prevalent differential multipoint standard in use today is TIA/EIA-485. The standard specifies an electrical signaling layer for multipoint operation, where up to 32 unit loads can be present on a single bus. TIA/EIA-485 specifies that drivers output a minimum of 1.5 V into a fully loaded bus. The specification requires receivers to have input thresholds of < 200 mV, while operating over a common-mode voltage range of -7 V to +12 V. TIA/EIA-485 supports moderate signaling rates of up to 50 Mbps, and you can use the standard for data transmission over distances of several kilometers. The attractive features of the 485 electrical layer have resulted in the standard being referenced in numerous higher-level standards including ANSI X3.129 (Intelligent Peripheral Interface), DIN 19245 (Profibus), ISO 11519 (Controller Area Network), and many others.

Small Computer Systems Interface (SCSI) is a family of multipoint standards developed for computer peripheral equipment. The SCSI standard is more than an electrical-layer specification, including pin assignment, connector definition, and protocol definition. Different variants of SCSI are available, relying upon differences in the electrical layer to provide speed, distance, or variations in the number of connected devices. Single-ended SCSI uses TTL-logic levels and is limited to 20 M-transfers/sec. High-voltage differential SCSI (HVD-SCSI) employs TIA/EIA-485 differential signaling to allow longer cable lengths and more devices to be connected to a bus than single-ended SCSI can support. HVD-SCSI signaling rates are limited to a maximum of 40 M-transfers/sec. Low-Voltage Differential SCSI (LVD-SCSI) is an adaptation of TIA/EIA-644 for use in SCSI systems. LVD-SCSI permits up to 16 devices to be connected to a multipoint bus, and supports a maximum signaling rate of 160 M-transfer/sec. LVD-SCSI receivers have to detect the correct logical state of the bus with as little as 30 mV of input signal, over an input common-mode range of 0.7 V to 1.8 V.

IEEE 1394 is a relatively new serial interface that is seeing rapid acceptance in the personal computer market, as well as entertainment electronics and video devices. Two implementations of IEEE 1394 are available, cabled 1394 and backplane 1394. Like SCSI, 1394 includes electrical- and mechanical-interface definition at the physical layer, and provides protocol definition as well. Backplane 1394 includes a physical multipoint-communication bus that can operate at rates up to 50 Mbps. Cabled 1394 acts as a virtual multipoint bus via the use of point-to-point connections and repeaters to relay incoming data from one node to the next. IEEE 1394a-2000 provides for a maximum data rate of 400 Mbps for cabled operations. IEEE 1394b, when finalized, will support a maximum data rate of 3.2 Gbps. 1394 drivers output a 400 mV differential signal, with a 1.6 V offset voltage. Receivers have a 100-mV threshold and can operate over a 1.1 V to 2.1 V common-mode input range.

The benefits from a comprehensive interface standard such as SCSI, 1394, or Universal Serial Bus (USB) arise when multiple vendors are involved in the development of numerous subsystems that require interfacing. When the development sources are more bounded, adherence to a pre-defined transmission protocol or connector pin assignments can be an unnecessary constraint.

Characteristics LVDS M-LVDS Maximum signaling rate 1.923 Gbps 500 Mbps Driver differential output signal 247 to 454 mV 480 to 650 mV Driver offset voltage 1.125 to 1.375 V 0.2 to 2.1 V Receiver ground shift tolerance ±1 V ±1 V Receiver input voltage threshold < 100 mV < 50 mV Receiver equivalent input impedance > 120 k > 120 k  Table 1: Comparison of electrical characteristics

The TIA TR-30.2 subcommittee that originally developed LVDS has been working on an enhancement to the 644 standard to support multipoint operation. Texas Instruments, National Semiconductor, and Fairchild all are participating in the standard's development. The M-LVDS standard, designated as PN4828, is currently in final revision, and release is expected this year. Given its legacy, the standard draws heavily on the electrical characteristics included in TIA/EIA-644. A standardized driver definition is included, as are specifications for two different classes of receivers. Like LVDS, M-LVDS is an electrical-layer definition only, and anticipates being referenced by a higher-level standard where designers want the benefits of multipoint LVDS circuits. While LVDS defined a maximum signaling rate of 1.923 Gbps, M-LVDS limits the maximum signaling rate to 500 Mbps. When multipoint operation is used, the presence of various drivers and receivers connected to the main bus line results in numerous stubs. These stubs act as discontinuities in the transmission line, distorting the signal the drivers provide. A rule of thumb is to limit the electrical length of the stubs to less than 15% of the transition time of signals on the bus. M-LVDS is intended for applications where a designer anticipates numerous stubs. To ease the design constraints associated with interface circuits connecting to the main bus line, M-LVDS limits the transition time allowed by compliant drivers. LVDS specified a minimum transition time of 260 picoseconds out of the driver, while the smallest transition time allowed by M-LVDS is 1 nanosecond, resulting in the maximum signaling rate of 500 Mbps.

M-LVDS drivers provide a typical differential output signal of 565 mV into a test load. This 565-mV output, into a 50- load, means that approximately 11.3 mA is delivered by an M-LVDS driver. When the actual M-LVDS application can be represented by a 50- load, the delivered signal is significantly increased over that available with LVDS. Many applications of M-LVDS will involve closely spaced backplanes, which results in heavier loads seen by the driver. The 11.3 mA output ensures that M-LVDS drivers still provide greater than 300 mV feeding a 30- load.

The M-LVDS standard includes the electrical characteristics of two different receivers, Type-1 and Type-2. Type-1 receivers have their input thresholds centered about 0 V. Type-1 requires thresholds of ±50 mV, which provides an additional improvement in noise margin over LVDS receivers. When the input voltage is less than 50 mV in magnitude, the receiver output is unspecified. Type-1 receivers are intended for maximum signaling rate lines. Type-2 receivers have their thresholds offset from 0 V, centered about 100 mV. When the input signal is less than +50 mV, a Type-2 receiver outputs a logic low. An input signal above +150 mV results in a Type-2 output of logic high. Type-2 receivers provide a known output when no input differential voltage is present. Type-2 receivers are intended for control lines, or lower signalling rate lines, where a defined response is desired when a sufficient input signal is not present.

When multiple drivers are on a single bus, driver contention can occur and must be accounted for in any multipoint standard. M-LVDS includes provisions to limit the maximum output voltage and current of active drivers. The standard limits active drivers to an output voltage between 0 V and 2.4 V. In the instance where multiple drivers are attempting to drive the bus simultaneously, the driver circuit has to decrease the current it supplies in order to keep the bus voltage within the specified limits. M-LVDS also limits the driver short-circuit current to 43 mA, thereby bounding the power that the driver can supply to the bus. Finally, the standard requires disabled drivers to meet the same leakage-current requirements with which the receivers must comply, namely the 120-k resistance on each pin. This high-impedance requirement for inactive drivers allows wired-OR signaling on the multipoint bus. Drivers can be wired-OR together, using the driver-enable controls as the input signals, and Type-2 M-LVDS receivers can detect the absence or presence of activity from any of the wired-OR drivers.

While each existing standard provides an optimum solution for some class of problems, the introduction of M-LVDS will provide an industry-standard, general-purpose, high-speed electrical-layer that extends the benefits of low-voltage differential signaling to multipoint designs. M-LVDS is appropriate for consideration in new designs where high speed and low power are critical. Existing designs intending to upgrade to reduce power or increase speed should also consider M-LVDS. The standard was designed to support multipoint operation in both cabled environments, where nodes are widely spaced, as well as densely populated backplanes. Applications with M-LVDS can realize 5X to 10X improvement in throughput over existing standards.