Processor Shoot-Out

It's like Dodge City out there, before law and order arrived. DSP and processor architectures are all over the place, with tremendous variations in structure and performance. Standard architectures are adding more muscle with added memory, peripherals, and chip-level multiprocessing. And new architectures are no longer constrained by past design rules needed to manage scarcity of transistor, silicon real estate, and pin-outs. Today's architectures have a wide-open town to strut their behavior. Last month's Embedded Processor Forum showcased the variety and performance potential of new and in-place architectures.

For at least 20 years, the silicon curve has been driving silicon-based processors. Silicon relentlessly moved up the silicon curve, doubling transistor resources, real estate, performance, or functionality every 18 months to two years. Now we are collecting the benefits of years of steady growth, like the power of compound interest, where after years of accumulation, the later years exhibit powerful growth.

For many years, the advantage lay with the standard architectures. The X86 architecture was the classic example. Many vendors developed alternative architectures to the clunky X86, especially during its 486 and early Pentium stages. But they were defeated by Intel, which invested heavily in silicon technology, building large state-of-the-art fabs and processes to easily move new chips into production.

Each innovative challenger ran into the silicon curve effect. By the time the new architecture was smoothed out and readied for production, the X86 had moved farther up the silicon curve, delivering higher performance. Each challenger found itself frozen lower down on the curve and basically outperformed by the wheezing X86 architecture. The new architecture's performance advantage was defeated by the silicon curve. A classic example of this design trap was the IBM/Motorola PowerPC, which failed to initially out power the Pentium, loosing access to the PC market except for MACs.

But times are a changing. Existing architectures still have the hometown advantage, but that lead is being whittled away by the potent combination of logic synthesis tools, advanced silicon, and available design blocks for new architectures. Designers can now synthesize large chips onto advanced silicon (0.18 to 0.13) filling in CPU, peripheral, and specialized processing cores. This design combination enables new architectures to piggyback onto the silicon curve, rather than be frozen in time on the curve like a fly in amber.

Moreover, these designers don't have to reinvent everything. Now, peripherals, memory, processor cores, specialized functions are available as hard or soft IP, readily synthesized into the design using current EDA tools. Yes, there are still IP integration problems, especially related to standardized buses. But designers are making do and turning out impressive architectures.

Examples of new high-performance DSP and communications system designs include:

• BOPS—a sophisticated MP design with multiple processing units that can deliver 20 or more parallel execution units with a complex results exchange.
• Chameleon—a dynamically reconfigurable design that integrates an ARC RISC with reconfigurable processor elements in a tiled array with multi-level interconnects.
• Transilica—an extensible MIPS + DSP coprocessor design that integrates hardware extensibility with a sophisticated tool and operating software chain.
• Dvine—a scalable MP configuration with six RISC CPUs and six vector processors, integrated with on-chip DRAM and a memory stream processor.

The traditional architectures are fighting back. They are rapidly moving up the silicon curve, moving to higher clock rates, lower power levels, and higher transistor counts. TI's C6x VLIW DSP, for example, is slated to hit 1 GHz with more on-chip memory and a tighter design. Other's like Lucent's new StarPro shifted to sophisticated on-chip MP. Its StarPro packs three StarCore VLIW DSPs onto a chip with a state-of-the-art split-transaction systems bus and 768 KB local memory.

Motorola has gone to low power MP operation with its SOC that integrates an M•CORE RISC and a StarCore VLIW into a wireless SOC for handsets. Both are low power processors. And Infinion has extended its TriCore with MP operation, with up to four processors on a split-transaction bus. It also extended its Carmel DSP with hardware plug-ins—adding up to four hardware functions to a regular DSP chip.

Traditionally, software—the availability and range of application and operating software—has acted as a brake on the wild proliferation of architectures. Software, the more expansive part of DSP development, has become the ultimate arbitrator of DSP chip success. No software, no design wins.

And so, the traditional DSP chips have the software advantage with large blocks of existing software tools, function libraries, application and operating software. But many of the newer DSPs have built software into their designs. For example, Tensilica is an extensible MIPS design, but the extensions reach into the software tool and operating software chains, with compilers and operating system tailored to match the design. The critical arenas will be those of application and library software. Only time will tell which architectures dominate, but right now architectures are in a state of flux, much like the Wild West before civilization settled in.