Taking the Frustration Out of Embedded Design

Mixed-logic hardware and embedded software has been a popular design-architecture choice ever since the advent of powerful and affordable microprocessors for board design in the early 1980s. This approach seemed to offer the best of two worlds—fast dedicated hardware algorithms, mixed with the flexibility and potential re-programmability of software. But realizing the end design came with a high price of long design cycles and proportionally higher costs—true hardware/software parallel design flows proved almost impossible. There were simply too many interdependent system flow points, with software designers waiting for prototype hardware on which to verify, and software verification pointing out hardware-redesign needs. Each iteration in this serial design, integrate, and then debug process proved to be time consuming, costly, and frustrating. Nevertheless, waiting at the end was the payoff of fast and flexible electronics products.

Fast-forward to today. Hardware design has come of age with the explosion of HDL-based logic design, synthesis, and implementation technologies, leading to hardware design that occurs faster, and with higher complexity products, than previously possible. Embedded-software design has taken a similar leap forward, with source-code size now doubling every two years. While the average software design size for an embedded project was 100,000 lines of code in 1995, in 2001 that average size had jumped to 1,000,000 lines of code, an order of magnitude increase over six years. The complexity of that code has changed as well, from standalone, unmanaged, fixed-function software, to networked, managed, and programmable embedded functions.

However, talk to the design managers of leading-edge embedded-design teams and you'll find that little has changed in their design flows. Although some inroads towards productive, embedded-system design flows have been made, true system design through the merger of logic-based and software-based design flows hasn't started to reach its potential. Why are we still waiting for the maturity of true embedded-design flows, and are there any advancements available that can move embedded-design along?

The point-tool offerings of EDA and software-design vendors are primarily directed at solving bottleneck embedded-design problems, most often in co-simulation, hardware and software emulation, and RTOS integration. By providing point solutions that join existing software and hardware design flows, users aren't yet able to reach a true embedded-system design flow. System-design experts also agree that a high-level language will not emerge as a solution with enough language constructs to satisfy both design-flow requirements for another two-to-six years.

However, there are now fully programmable system platforms available introducing integrated-system components such as buried processor cores, DSP capability, customizable silicon-IP, and an abundance of on-board RAM. With these platforms, the old rules have been changed and there are new options available for us. There is an embedded solution on the horizon that takes existing software and hardware design flows and integrates them onto a unified platform. This solution is coming from a familiar source of innovation, the FPGA vendors. These "off-the shelf" solutions link best-of-class programmable-logic design with industry-leading software design and RTOS offerings.

"System smart" IDEs, integrated development environments, supporting hardware, software, and IP-generation flows, will bridge the productivity gap which currently exists between software-only and hardware-only IDE methodologies and their rigid IP libraries. The ability to jump right into real-time debug on existing programmable-system devices and reference boards will expedite the time-to-visualization and functional validation of designs while reducing the currently harsh dependency on simulation-only environments. Innovation such as on-chip interactive software debug without the need to re-execute FPGA place-and-route tools will help make true hardware/software system design a reality as well.

More importantly, solutions being announced within the coming months will deliver a true system-design flow supporting on-demand architectural synthesis, high-level language compilation, and true co-design and co-verification flows through the integration of leading partner technology and core-design tools. New co-design technology expands the support for programmable systems by enabling a variety of engineers to define an entire system in ANSI-C to obtain the most optimal implementation by rapidly partitioning and repartitioning between hardware and software modules. A repartition is just a compile-time switch, which enables one to profile and translate back and forth between hardware/software implementations in a matter of minutes rather than days or weeks. The result is user customization, allowing a tradeoff between features and design size. Another benefit is taking advantage of the performance optimization achievable by greatly accelerating software-module serial execution in parallel hardware implementations.

These solutions deliver an optimum system-development platform, with true parallel hardware/software design flows, and a logic platform that can be quickly and easily debugged, erased, and reprogrammed in a matter of minutes, both in hardware through the FPGA and software, delivering the ideal system-design platform. Fully programmable system devices have finally enabled this next step in the evolution of system design previously restricted by rigid platforms and the isolation of hardware/software tool flows.

FPGA vendors also have the resources, business and market structure, and partnerships to deliver the integrated design solution required by the end user. The silicon innovation that melds dedicated logic and the embedded processor has already taken place—these devices are in the marketplace. Since FPGA silicon revenue is the prime funding behind programmable software R&D budgets, there are no roadblocks left in the way of full co-design and co-verification integration. The design-flow innovation now comes full-circle, driving more device usage and, ultimately, leading to the better system-design flows needed by embedded engineers.

Richard Sevcik is the senior vice president in charge of the FPGA Product Group and the Intellectual Property, Services and Software Group at Xilinx. He is currently responsible for ensuring the delivery of the company's leading-edge FPGAs, which include the Virtex and Spartan FPGA families. Mr. Sevcik is also responsible for all aspects of software tools and intellectual-property cores at Xilinx, including product development, marketing, and the company's support organization, which provides application and design services as well as training for customers worldwide. Sevcik was appointed to the Xilinx Board of Directors in April 2000.

Mr. Sevcik joined Xilinx in 1997 from Hewlett-Packard, where he served as group general manager of HP's Systems Technology Group. He received his bachelor's degree in engineering physics from the University of Illinois and his masters degree in solid-state physics from Northwestern University.