How Much Bandwidth Does Your Logic Analyzer Need?

There is much confusion when it comes to discussing bandwidth and logic analyzers. Traditionally logic analyzers are thought of as a purely digital measurement tool. However, as datarates increase and rise times shrink, designers are being forced to understand the analog characteristics of this tool. One of the biggest problems that designers face is ensuring that their verification tools are able to function at these higher frequencies. Factors such as the equipment's bandwidth and loading can cause false negatives and break systems when not fully understood. It is imperative that digital system designers can trust their logic analyzer in order to achieve the fastest time-to-market. As frequencies continue to rise, the logic analyzer front-end needs to be treated with the same analog delicateness as an oscilloscope.

There are two main considerations that engineers must understand when analyzing the bandwidth of their system and validation tools. The first is the frequency components present in their digital signals on their PCB and how that relates to their logic analyzer's bandwidth. The second is how the probe loading will interact with these frequencies. Both considerations come down to the theory of how digital signals are translated into analog metrics and how to use these metrics to analyze whether a successful measurement can be made. The following sections will discuss the three techniques to translate a digital signal into analog metrics. The three translations are rise-time-to-bandwidth, toggle-rate-to-bandwidth, and pulse-width-to-bandwidth. Once a digital signal can be described in terms of bandwidth, then the loading and logic analyzer bandwidth can be easily analyzed.

Figure 1:  Solving an RC circuit in both the time and frequency domain results in a linear relationship between rise-time and bandwidth.

The first step in this derivation is to solve the circuit in the time domain assuming it is being driven with a unit step (u(t)). The general solution to this circuit is given by:

  (1)

Since rise-time is defined as the time it takes to transition from 10% to 90% of V_OUT, we can solve the equation to get two separate solutions. The first solution is the time it takes to transition from 0 volts to 10% of V_OUT. To accomplish this, V_IN is set to 1 volt and V_OUT is set to 0.1 volts. The second solution is obtained in the same way except that V_OUT is set to 0.9 volts. Since rise-time is defined as the time between these two solutions, the results are simply subtracted and yield a rule of thumb for the rise-time of an RC circuit.

  (2)

The second step of this derivation is to solve the same RC circuit in the frequency domain. The general solution to this circuit is given by:

  (3)

Since bandwidth is defined as the frequency at which the magnitude of the response is attenuated by 30%, then this expression can be solved to generate a rule of the thumb.

  (4)

Now that we have general expression for rise-time and bandwidth in terms of resistance and capacitance, we can combine the two expressions to yield a single linear relationship. This expression can now be used to quickly convert between the rise-time of a digital signal and the frequency components that the rise-times possesses.

  (5)

  (6)

A rule of thumb commonly used in digital systems is that the system must have enough bandwidth to capture the 3^rd harmonic of the digital pulse train. When relating this to the Shaw function, the third harmonic refers to the third impulse in the frequency domain. Figure 2 illustrates the transform and how the rule of thumb relates.

Figure 2:  A periodic signal in the time domain is represented as a series of impulses spaced at the period of the signal. This translates into a series of impulses in the frequency domain that occur at the integer evaluation of (1/period).

The total bandwidth needed for a periodic signal can be expressed as:

  (7)

  (8)

The sinc function produces a series of envelopes as the frequency increases. The zero crossings of the sinc function will occur at integer evaluations of the sinc function argument. In this case it will be evaluated at integer evaluations of (1/width). Figure 3 shows how a time domain pulse is represented in the frequency domain.

Figure 3:  A pulse in the time domain transforms to a sinc function in the frequency domain. A rule of thumb is that the system needs enough bandwidth to capture half of the second sinc envelope.

As mentioned before, a common rule of thumb is that the system needs enough bandwidth to capture the third harmonic of the digital pulse train. In Fourier representation, a digital pulse train is described as a rectangle function convolved with the Shaw function. In the time domain, this produces a series of pulses repeating at the maximum toggle rate of the data stream. The pulse is represented using the rectangle function and the periodicity of the data stream is represented with the Shaw function. The convolution operator combines the two functions in the time domain. In the frequency domain, the rectangle function transforms into the sinc function, the Shaw function transforms into another Shaw function and the convolution operator transforms into a multiplication operation. The multiplication of the Shaw and sinc functions in the frequency domain has the effect of producing Shaw impulses that are bound by the envelope of the sinc function.

  (9)

For a 50% duty cycle pulse train, the Shaw impulses will occur at every integer evaluation of (1/period). The envelope of the sinc function will have zero crossings at every integer evaluation of (1/width), which will cancel out the Shaw impulses at these frequencies. What is left are the Shaw impulses evaluated at every odd integer evaluation of (1/period). The first odd integer impulse evaluation is called the fundamental frequency. The remaining odd integer impulse evaluations are called harmonics. As stated before, the system needs enough bandwidth to capture the third harmonic of the pulse train. In the special case just described, this occurs in the middle of the second sinc envelope. The assumption that this is sufficient bandwidth can be extended as the pulse width decreases. It can now be said that a system needs enough bandwidth to capture 1/2 of the second sinc envelop to reliably deliver the associated pulse. This relationship can be written as:

  (10)

  (11)

If we use the example in the previous section, we can determine the maximum capacitance that the probe can present on the system without sever degradation. In the above example, the system had 1.875 GHz of bandwidth present in its digital signals. Plugging this into the above expression returns the maximum probe capacitance that can be tolerated by the system. In this case it is 3.4pF.

Figure 4:  The capacitive load of the logic analyzer probe forms an RC filter with the impedance of the transmission line. In order to not disturb the signal being probed, the 3dB frequency of the probe's RC load must be larger than the highest analog frequency present in the digital pulse train.