Tessolve evaluates DeFacTo RTL testability solution

PARIS — DeFacTo Technologies SA, French provider of Design-for-Test solutions at RTL, announced that Tessolve, Indian-based test and IC packaging services company, has evaluated HiDFT-Scan, a RTL testability sign-off solution.

DeFacTo (Moirans, France) claimed its HiDFT-Scan software solution analyzes register transfer level (RTL) IC and SoC designs. The program creates appropriate RTL scan test structures and inserts them into the RTL design.

DeFacTo started shipping its HiDFT-Scan for evaluation at selected chip designers including LSI Logic Corp. (Milpitas, California) and STMicroelectronics NV (Geneva, Switzerland) in October 2007.

Chandra sekhar Gandu, Tessolve's Design-for-Test manager, explained that implementing complete testability at RTL level enabled the company to detect key testability issues and improve coverage early in design phase.

He continued: "Our evaluation has proven that the HiDFT-Scan flow helps detecting major testability problems at RTL with a very good accuracy, close to 0.5 percent in comparison to a gate-level flow. HiDFT-Scan has robust set of Design Rule Checks and enables new RTL DFT verification capabilities. We expect to take advantage from this flow with our future customers to be much more proactive in our design flow."

Based in Bangalore, India, Tessolve provides solutions in DFT, test engineering, test hardware development, package assembly and failure analysis. It employs about 400 people.

In July 2008, Applied Ventures LLC, the investment arm of Applied Materials Inc., invested in Tessolve Services an undisclosed amount.