Darpa funds power-aware architecture development

Darpa funds power-aware architecture development
EVANSTON, Ill. — Researchers at the electrical and computer engineering department of Northwestern University have received a $2 million grant from the Defense Advanced Research Projects Agency (Darpa) to develop new techniques for minimizing the power consumption of computer systems.

Motorola Inc. and Cadence Design Systems Inc. are partners in the research, and will have access to the findings.

The power consumption of processors and peripherals is a major concern in portable equipment like cellular handsets, laptops, palmtops and two-way radios, said Prith Banerjee, the Northwestern professor who will head the project. But in recent years power-vs.-performance trade-offs have also applied to servers and mainframes, he said, because of concerns about electric-power costs, he said.

Military applications and platforms — of special interest to Darpa — have an urgent, growing need for power-efficient computing and communications. Power efficiency, in Darpa's view, would let existing platforms perform new missions and extend their mission time lines — sometimes dramatically.

Called Pact, for "power-aware architecture and compilation techniques," the Northwestern project will develop power-savvy architectural schemes along with associated compilers and CAD tools. The goal is to take applications written in the C programming language and generate power- and performance-efficient code for embedded computing systems utilizing power-aware architectural techniques, Banerjee said.

The Pact project proposes a cross-coupling of computer architectures and compilers with the idea of minimizing power consumption. The traditional goal is to reduce the number of clock cycles a processor goes through, and the amount of work accomplished with each cycle, said Banerjee. But additional power savings could be found by coupling the computer architecture to the capabilities of the compiler, and vice versa.

The Pact team — which includes Majid Sarrafzadeh, Alok Choudhary, Andreas Moshovos, Horace Yuen and 10 Northwestern graduate students — hopes to develop technologies that can reduce the total energy consumption in specific applications by factors of 10 to 100 over conventional, non-power-aware architectures.

Banked caches and memory hierarchies, clock gating, voltage and frequency scaling and information encoding are the best places to look for architectural-level power savings, Banerjee said. Power-aware compilation techniques, similarly, will examine automated mapping and scheduling of various library functions.

The project is scheduled to last until Sept. 30, 2003.