Researchers demo wireless chip-interconnect scheme

Among those asking the question is a research group from the University of Florida at Gainesville that has responded with a working test chip that uses radio frequency to distribute a clock signal at 7.4 GHz. The technology also could prove useful in distributing a synchronous clock across ICs on a module.

The program has been under way for three years, supported by modest funding — about $150,000 per year — from Semiconductor Research Corp. At last month's International Solid-State Circuits Conference in San Francisco, associate electronics engineering professor Kenneth O, and two graduate students participating in the project, Brian Floyd and Kihong Kim, described a successful test chip with a limited number of active circuits between the transmit and receive modules on the edges of the die.

"We are basically creating a new architecture," O said. "The goal is to investigate the trade-off between driving large wires across the chip, as in a conventional approach, or the ability with this clock transmitter to synchronize the clock across a large die size, or even to break the bottleneck between 2D and 3D structures."

"People are somewhat skeptical whether this approach will be able to overcome the noise issue," said Bob Havemann, an interconnect expert with Texas Instruments Inc. who is now on assignment to International Sematech here. "But the chip sizes are not getting any smaller, and unless the industry moves to an asynchronous clock, the long interconnects for the clock are going to be a problem."

Collision course

"My biggest concern is that the industry is not doing enough to understand the design issues in these very high-frequency circuits," Havemann said. "We are on a collision course between digital and RF as we move to a gigahertz and beyond." Havemann likened the Florida research to the communications systems of Star Trek's Borg spaceship, in which everyone on board is connected to a wireless comms system.

O acknowledged that maintaining a good signal-to-noise ratio is the major challenge in sending a radio signal across a die with millions of switching transistors and interference from metal structures.

The test chip includes antennas measuring 2 millimeters long and 10 micrometers wide, fabricated in the metal-five layer and separated from the substrate by about 7 micrometers of oxide. "What we are trying to do is get a lower clock skew, but it is not clear if that will be possible," O said.

Floyd said the next step is to increase the frequency of the transmit and receive circuits to 20 GHz or higher, with 30 GHz as a "conservative goal" even as the antennas get smaller. While it will not be difficult to increase the frequency of the antennas in more advanced design rules, synchronization across the chip may present a challenge, he said.

The structures include low-noise amplifiers and buffers that shift the voltage level to a series of frequency dividers. To achieve an acceptable signal-to-noise ratio, the high-frequency transmit signal is divided — in this case in an 8:1 architecture — to the local clock frequency. But O said it remains to be seen whether the approach can overcome the signal-to-noise problem.

The Florida project is competing with efforts at Vanderbilt University and elsewhere to use optical interconnects, but the Florida group is ahead in the sense that it has demonstrated send and receive capabilities. Any "free space" interconnect scheme, in which a signal can be "seen" by all of the circuits on a device, presents shielding and other challenges.

Also, building the tiny antenna and receive modules in an RF interconnect approach takes up silicon real estate. Optical interconnect has a similar challenge: Building an on-chip laser requires, in most cases, a compound semiconductor process.