Networking IC packs two 64-bit CPUs

Irvine, Calif. - Broadcom Corp. is sampling a 60 million-transistor SiByte system-on-chip for Internet infrastructure applications.

The BCM1250 includes two 64-bit MIPS CPUs, a high-speed memory subsystem and I/O peripherals. Its 256-bit-wide ZBus delivers up to 100 Gbits/second of on-chip bus bandwidth. The part includes 512 kbytes of Level 2 cache and a DDR memory controller that supports up to 2 Gbytes of memory. Its processor can support up to 50 Gbits/s of peak memory bandwidth.

Integrated I/O includes three 10/100/1,000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66-MHz PCI bridge, support for HyperTransport, a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug.

In sample quantities, the price is $649. Production is planned for the fourth quarter.

Call (949) 450-8700
www.Broadcom.com
EETInfo No. 616